Threshold voltage roll-up/roll-off characteristic control in sub-0.2-μm single workfunction gate CMOS for high-performance DRAM applications

IEEE Transactions on Electron Devices

Volumn 49, Issue 2, 2002, Pages 308-313

  Inaba, Satoshi ^a,b,c   Katsumata, Ryota ^b,c   Akatsu, Hiroyuki ^d   Rengarajan, Rajesh ^b,e   Ronsheim, Paul ^d   Murthy, Cheruvu S ^d   Sunouchi, Kazumasa ^a,b,c   Bronner, Gary B ^a,d  

^a IEEE   (Japan)

^b Toshiba America Inc   (United States)

^c TOSHIBA CORPORATION   (Japan)

^d IBM MICROELECTRONICS   (United States)

^e IBM   (United States)

Author keywords

Buried channel; Halo structure; MOSFETs; N 2 implant; pFET; Silicon; Single workfunction gate; V t variation; Well RTA

Indexed keywords

BURIED CHANNEL; GATE OXIDATION; HALO IMPLANT; REVERSE SHORT CHANNEL EFFECT; SHORT CHANNEL EFFECT; SINGLE WORKFUNCTION GATE; SOURCE DRAIN IMPLANT; VARIATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; NITROGEN; OPTIMIZATION; OXIDATION; RAPID THERMAL ANNEALING; SECONDARY ION MASS SPECTROMETRY; SILICON WAFERS; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0036475493     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.981222     Document Type: Article

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