-
2
-
-
0031336414
-
Efficient coupled noise estimation for on-chip interconnects
-
A. Devgan, "Efficient Coupled Noise Estimation for On-Chip Interconnects," Int. Conf. Computer-Aided Design, pp. 147-151, 1997.
-
(1997)
Int. Conf. Computer-Aided Design
, pp. 147-151
-
-
Devgan, A.1
-
3
-
-
0025414182
-
Asymptotic waveform evaluation for timing analysis
-
Apr.
-
L. T. Pillage and R. A. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Trans. CAD, vol.9, pp. 352-366, Apr. 1990.
-
(1990)
IEEE Trans. CAD
, vol.9
, pp. 352-366
-
-
Pillage, L.T.1
Rohrer, R.A.2
-
4
-
-
0029308198
-
Efficient linear circuit analysis by pade approximation via the lanczos process
-
May
-
P. Feldmann and R. W. Freund, "Efficient Linear Circuit Analysis by Pade Approximation Via the Lanczos Process," IEEE Trans. CAD, vol. 14, pp. 639-649, May 1995.
-
(1995)
IEEE Trans. CAD
, vol.14
, pp. 639-649
-
-
Feldmann, P.1
Freund, R.W.2
-
5
-
-
0032139262
-
PRIMA: Passive reduced-order interconnect macromodeling algorithm
-
A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm," IEEE Trans. CAD, vol. 17, pp. 645-654, 1998.
-
(1998)
IEEE Trans. CAD
, vol.17
, pp. 645-654
-
-
Odabasioglu, A.1
Celik, M.2
Pileggi, L.T.3
-
6
-
-
0032681122
-
Harmony: Static noise analysis of deep submicron digital integrated circuits
-
K. L. Shepard, V. Narayanan, and R. Rose, "Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits," IEEE Trans. CAD, vol. 18, pp. 1132-1150, 1999.
-
(1999)
IEEE Trans. CAD
, vol.18
, pp. 1132-1150
-
-
Shepard, K.L.1
Narayanan, V.2
Rose, R.3
-
7
-
-
0033685443
-
ClariNet: A noise analysis tool for deep submicron design
-
R. Levy, D. Blaauw, G. Braca, et al., "ClariNet: A Noise Analysis Tool for Deep Submicron Design," Design Automation Conference, pp. 233-238, 2000.
-
(2000)
Design Automation Conference
, pp. 233-238
-
-
Levy, R.1
Blaauw, D.2
Braca, G.3
-
8
-
-
0031099379
-
Crosstalk reduction for VLSI
-
Mar.
-
A. Vittal and M. Marek-Sadowska, "Crosstalk Reduction for VLSI," IEEE Trans. CAD, vol. 16, pp. 290-297, Mar. 1997.
-
(1997)
IEEE Trans. CAD
, vol.16
, pp. 290-297
-
-
Vittal, A.1
Marek-Sadowska, M.2
-
9
-
-
0033320052
-
Crosstalk in VLSI interconnects
-
Dec.
-
A. Vittal, L. H. Chen, M. Marek-Sadowska, et al., "Crosstalk in VLSI Interconnects," IEEE Trans. CAD, vol. 18, pp. 1817-1824, Dec. 1999.
-
(1999)
IEEE Trans. CAD
, vol.18
, pp. 1817-1824
-
-
Vittal, A.1
Chen, L.H.2
Marek-Sadowska, M.3
-
10
-
-
84949743939
-
Improved crosstalk modeling for noise constrained interconnect optimization
-
J. Cong, D. Z. Pan, and P. V. Srinivas, "Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization," ASP-DAC, pp. 373-378, 2001.
-
(2001)
ASP-DAC
, pp. 373-378
-
-
Cong, J.1
Pan, D.Z.2
Srinivas, P.V.3
-
11
-
-
0035333780
-
Aggressor alignment for worst-case crosstalk noise
-
May
-
L. H. Chen and M. Marek-Sadowska, "Aggressor Alignment for Worst-Case Crosstalk Noise," IEEE Trans. CAD, vol. 20, pp. 612-621, May 2001.
-
(2001)
IEEE Trans. CAD
, vol.20
, pp. 612-621
-
-
Chen, L.H.1
Marek-Sadowska, M.2
-
12
-
-
0034841570
-
Driver modeling and alignment for worse-case delay noise
-
S. Sirichotiyakul, D. Blaauw, C. Oh, et al., "Driver Modeling and Alignment for Worse-Case Delay Noise," Design Automation Conference, pp. 720-725, 2001.
-
(2001)
Design Automation Conference
, pp. 720-725
-
-
Sirichotiyakul, S.1
Blaauw, D.2
Oh, C.3
-
13
-
-
0024906813
-
Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation
-
P. R. O'Brien and T. L. Savarino, "Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation," Int. Conf. Computer-Aided Design, pp. 512-515, 1989.
-
(1989)
Int. Conf. Computer-Aided Design
, pp. 512-515
-
-
O'Brien, P.R.1
Savarino, T.L.2
-
14
-
-
0028756124
-
Modeling the effective capacitance for the RC interconnect of CMOS gates
-
Dec.
-
J. Qian, S. Pullela, and L. T. Pillage, "Modeling the Effective Capacitance for the RC Interconnect of CMOS Gates," IEEE Trans. CAD, vol. 13, pp. 1526-1535, Dec. 1994.
-
(1994)
IEEE Trans. CAD
, vol.13
, pp. 1526-1535
-
-
Qian, J.1
Pullela, S.2
Pillage, L.T.3
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