Transition time modeling in deep submicron CMOS

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 11, 2002, Pages 1352-1363

  Maurine, P ^a   Rezzoug, M ^b   Azemard, N ^a   Auvergne, D ^a  

^a Laboratoire IRM de Montpellier   (France)

^b Unilog   (France)

Author keywords

Deep submicron; Modeling; Timing analysis

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC INVERTERS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SHORT CIRCUIT CURRENTS;

CAPACITIVE LOAD; DEEP SUBMICRON; PROPAGATION DELAY TIME; SHORT CIRCUIT POWER DISSIPATION; TIMING ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 0036864704     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.804088     Document Type: Article

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