Poly Flanked VDMOS (PFVDMOS): A superior technology for superjunction devices

PESC Record - IEEE Annual Power Electronics Specialists Conference

Volumn 4, Issue , 2001, Pages 2156-2159

  Gan, K P ^a   Liang, Y C ^a   Samudra, G S ^a   Xu, S M ^a   Yong, L ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Superjunction MOS structure; VDMOS

Indexed keywords

POLY FLANKED VERTICAL DOUBLE DIFFUSION TECHNOLOGY; SUPERJUNCTION DEVICES;

ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; INTERDIFFUSION (SOLIDS); SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

MOSFET DEVICES;

EID: 0034795057     PISSN: 02759306     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PESC.2001.954439     Document Type: Conference Paper

References (11)

1. A new generation of high voltage MOSFETs breaks the limit line of silicon
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3. Which is cooler, trench or multi-epitaxy?
4. A novel vertical deep trench RESURF DMOS (VTR-DMOS)
5. Simulated superior performance of semiconductor superjunction devices
6. Optimum doping profile for minimum ohmic resistance and high breakdown voltage
7. Selective epitaxy growth of Silicon and some potential applications