Precise interrupts

IEEE Micro

Volumn 16, Issue 1, 1996, Pages 58-67

  Moudgill, Mayan ^a,c,d,e   Vassiliadis, Stamatis ^{b,e,f,g,h,i,j}  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c VLIW Development Group

^d INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^e Indian Institute of Technology ^*

^f IBM   (United States)

^g Mid Hudson Valley Laboratory   (United States)

^h Glendale Laboratory   (United States)

ⁱ POLITECNICO DI MILANO   (Italy)

^j UNIVERSITY OF NAMUR   (Belgium)

more..

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0001944474     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.482313     Document Type: Article

References (12)

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2. IBM System/370 Extended Architecture Principles of Operation, IBM Corp., Poughkeepsie, N.Y., 1983.
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6. C.-J. Wang and F. Emmett, "Precise Interruptions in RISC Pipelines," IEEE Micro, Vol. 13, No. 4, Aug. 1993, pp. 36-43.
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8. CDC CYBER 200 Model 205 Computer System Hardware Reference Manual, Control Data Corp., Arden Hills, Minn., 1981.
9. G.F. Grohoski, "Machine Organization of the IBM RISC System/6000 Processor," IBM J. Research and Development, Vol. 34, No. 1, Jan. 1990, pp. 37-58.
10. Alpha Architecture Handbook, Digital Equipment Corp., Maynard, Mass., 1992.
11. IBM RT PC Hardware Technical Reference, IBM Corp., Austin, Tex., 1986.
12. H.C. Torng and M. Day, "Interrupt Handling for Out-of-Order Execution Processors," IEEE Trans. Computers, Vol. 42, No. 1, Jan. 1993, pp. 122-127.