Skewed CMOS: Noise-immune high-performance low-power static circuit family

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 423-426

  Solomatnikov, Alexandre ^a   Somasekhar, Dinesh ^b   Roy, Kaushik ^a  

^a Purdue University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOMINO CIRCUIT; DOMINO LOGIC; DYNAMIC NOISE; LOW-VOLTAGE APPLICATIONS; NOISE MARGINS; PEAK CURRENTS; PIPELINED MULTIPLIERS; STATIC CIRCUIT;

LOW POWER ELECTRONICS;

LOGIC CIRCUITS;

EID: 84893773793     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D. Somasekhar, "Power and dynamic noise considerations in high performance CMOS VLSI design", Ph.D. Thesis, Purdue University, August 1999.
2. D. W. Dobberpuhl et al., "200-MHz 64-bit Dual-issue CMOS microprocessor", Digital Technical Journal, Vol. 4, No. 4, pp. 1-19, Special Issue, 1992.
3. F. Murabayashi et al., "2.5V CMOS Circuit design technique for a 200 MHz superscalar RISC processor", IEEE Journal of Solid State Circuits, vol. 31, No. 7, pp. 972-980, July 1996.
4. D. Somasekhar, S. H. Choi, K. Roy, Y. Ye, V. De, "Dynamic Noise Analysis in Precharge-Evaluate Circuits", accepted to Design Automation Conference 2000.