13.3ns double-precision floating-point ALU and multiplier

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1995, Pages 466-470

  Yamada, H ^a   Hotta, T ^a   Nishiyama, T ^a   Murabayashi, F ^a   Yamauchi, T ^a   Sawamoto, H ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; DIGITAL ARITHMETIC; MULTIPLYING CIRCUITS; PERFORMANCE; SHIFT REGISTERS; TECHNOLOGY;

ARITHMETIC LOGIC UNIT; CARRY SELECT ADDITION; FLOATING POINT NUMBER; NOISE TOLERANT PRECHARGE CIRCUIT;

DIGITAL CIRCUITS;

EID: 0029476354     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)