Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1998, Pages 245-249

  Alvandpour, Atila ^a   Larsson Edefors, Per ^a   Svensson, Christer ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ENERGY UTILIZATION; ESTIMATION; SHORT CIRCUIT CURRENTS; VOLTAGE MEASUREMENT;

POWER ESTIMATION; SHORT CIRCUIT POWER CONSUMPTION;

VLSI CIRCUITS;

EID: 0031623375     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/280756.280919     Document Type: Conference Paper

References (8)

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2. N. Hedenstierna K. O. Jeppson CMOS Circuit Speed and Buffer Optimization IEEE Trans. on CAD CAD-6 2 270 281 March 1987
3. T. Sakurai A. R. Newton Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and other Formulas IEEE JSSC 25 2 584 594 April 1990
4. S. R. Vemuru N. Scheinberg Short-Circuit Power Dissipation Estimation for CMOS Logic Gates IEEE Trans. on CAS 41 11 762 765 Nov. 1994
5. Y. P. Tsividis Operation and modeling of the MOS transistors 1987 McGraw-Hill New York
6. N. G. Einspruch G. Gildenblat Advanced MOS Device Physics 18 1989 Academic Press
7. M. Shur Physics of Semiconductor Devices 1990 Prentice Hall