The COB stack DRAM cell at technology node below 100 nm - Scaling issues and directions

IEEE Transactions on Semiconductor Manufacturing

Volumn 15, Issue 2, 2002, Pages 137-143

  Kim, Kinam ^a,b   Jeong, Moon Young ^b  

^a IEEE   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

Cell capacitance; Cell transistor; DRAM; Junction leakage current

Indexed keywords

CELL TRANSISTORS; MEMORY CELL CAPACITANCES;

CAPACITANCE; LEAKAGE CURRENTS; NANOTECHNOLOGY; SEMICONDUCTOR JUNCTIONS; TRANSISTORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0036565440     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.999584     Document Type: Article

References (12)

1. Highly manufacturable 4 Gb DRAM using using O.11 μm DRAM technology
2. Highly manufacturable and high performance SDR/DDR 4 Gb DRAM
3. DRAM technology perspective for gigabit era
4. TH fluctuation in DRAM cell transistors due to neighboring drain/source electric field penetration
5. High-performance cell transistor design using metallic shield embedded shallow trench isolation (MSE-STI) for Gbit generation DRAM's
6. Performance fluctuations of 0.10 μm MOSFETs - Limitation of 0.1 μm ULSI's
7. 4-liner STI for the improvement of data retention time in gigabit density DRAM and beyond
8. On the retention time distribution of dynamic random access memory (DRAM)
9. Local-field-enhancement model of DRAM retention failure
10. A strategy for long data retention time of 512 Mb DRAM with 0.12 μm design rule
11. Scaling guideline of DRAM memory cells for maintaining the retention time
12. 3 thin-film capacitors for Gbit-scale DRAMs