A strategy for long data retention time of 512Mb DRAM with 0.12μm design rule

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue TECHNOLOGY SYMP., 2001, Pages 27-28

  Uh, H S ^a   Lee, J K ^a   Lee, S H ^a   Ahn, Y S ^a   Lee, H O ^a   Hong, S H ^a   Lee, J W ^a   Koh, G H ^a   Jeong, G T ^a   Chung, T Y ^a   Kim, K ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FIELD EFFECTS; ION IMPLANTATION; LEAKAGE CURRENTS; OPTIMIZATION; SEMICONDUCTING SILICON; TRANSISTORS;

DATA RETENTION TIME;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034798645     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)