Intelligent signal processing based on a psychologically-inspired VLSI brain model

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E85-A, Issue 3, 2002, Pages 600-609

  Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

Floating gate MOS; Image recognition; Neuron MOS; Psychological brain model; Vector quantization; VLSI

Indexed keywords

ALGORITHMS; ARTIFICIAL INTELLIGENCE; BRAIN MODELS; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; MAXIMUM LIKELIHOOD ESTIMATION; MOSFET DEVICES; NEURAL NETWORKS; REAL TIME SYSTEMS; SILICON WAFERS; VECTOR QUANTIZATION; VLSI CIRCUITS;

ASSOCIATIVE PROCESSOR ARCHITECTURE; IMAGE RECOGNITION; INTELLIGENT SIGNAL PROCESSING; MOBILE APPLICATIONS; PSYCHOLOGICAL BRAIN MODEL;

DIGITAL SIGNAL PROCESSING;

EID: 0036522722     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (43)

1. G. Moor, "Progress in digital integrated electronics," IEDM Tech. Dig., pp. 11-13, 1975.
2. T. Shibata and T. Ohmi, "Neural microelectronics," Technical Digest, International Electron Devices Meeting (IEDM), pp. 337-342, Washington D.C., 1997.
3. T. Shibata, T. Nakai, N, M. Yu, Y. Yamashita, M. Konda, and T. Ohmi, "Advances in neuron-MOS applications," ISSCC Dig. Technical Papers, SA 18.4, pp. 304-305, Feb. 1996.
4. T. Yamashita, T. Shibata, and T. Ohmi, "Neuron MOS winner-take-all circuit and its application to associative memory," ISSCC Dig. Technical Papers, FA 15.2, pp. 236-237, Feb. 1993.
5. T. Shibata, and T. Ohmi, "A functional MOS transistor featuring gate-level weighted sum and threshold operations," IEEE Trans. Electron Devices, vol. 39, no. 6, pp. 1444-1455, 1992.
6. W. S. McCulloch and W. Pitts, "A logical calculus of the ideas immanent in nervous activity," Bull. Math. Biophys., vol. 5, p. 115, 1943.
7. T. Shibata and T. Ohmi, "Neuron MOS binary-logic integrated circuits: Part I, Design funda-mentals and soft-hardware-logic circuit implementation," IEEE Trans. Electron Devices, vol. 40, no. 3, pp. 570-576, 1993.
8. T. Shibata and T. Ohmi, "Neuron MOS binary-logic integrated circuits: Part II, Simplifying techniques of circuit configuration and their practical applications," IEEE Trans. Electron Devices, vol. 40, no. 5, pp. 974-979, 1993.
9. T. Shibata, K. Kotani, and T. Ohmi, "Real-time reconfigurable logic circuits using neuron MOS transistors," ISSCC Dig. Technical Papers, FA 15.3, pp. 238-239, Feb. 1993.
10. W. Weber, S.J. Prange, R. Thewes, E. Wohlrab, and A. Luck, "On the application of the neuron MOS transistor principle for modern VLSI design," IEEE Trans. Electron Devices, vol. 43, no. 10, pp. 1700-1708, 1996.
11. K. Ike, K. Hirose, and H. Yasuura, "A module generator of 2-level neuron MOS circuits," Proc. 4th International Conference on Soft Computing, Methodologies for the Conception, Design, and Application of Intelligent Systems, pp. 109-112, World Scientific, Singapore, 1996.
12. T. Shibata, H. Kosaka, H. Ishii, and T. Ohmi, "A neuron MOS neural network using self-learning-compatible synapse circuits," IEEE J. Solid-State Circuits, vol.30, no.8, pp.913-922, 1995.
13. H. Kosaka, T. Shibata, H. Ishii, and T. Ohmi, "An excellent weight-updating-linearity EEPROM synapse memory cell for self-learning neuron-MOS neural networks," IEEE Trans. Electron Devices, vol.42, no.1, pp.135-143, 1995.
14. J. Nakamura and E.R. Fossum, "Image sensor with image smoothing capability using a neuron MOSFET," in Charge-Coupled Device and Solid State Optical Sensors IV, Proc. SPIE, vol. 2172, pp. 30-37, 1994.
15. M. Okebe, M. Akazawa, and Y. Amemiya, "νMOS cellular-automaton devices for intelligent image sensors," Proc. 5th International Conference on Soft Computing and Information/Intelligent Systems, pp. 16-20, Oct. 1998
16. Iizuka, Fukukoka, "Methodologies for the conception, design and applications of soft computing," vol. 1, ed. T. Yamakawa and G. Matsumoto, pp. 113-117.
17. S. Jung, R. Thewes, T. Scheiter. K.F. Groser, and W. Weber, "A low-power and high-performance MOS fingerprint sensing and encoding architecture," IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 978-984, 1999.
18. H.R. Mehrvarz and C.Y. Kwok, "A large-input-dynamic-range multi-input floating-gate MOS four-quadrant analog multiplier," IEEE J. Solid-State Circuits, vol. 31, no. 8, pp. 1123-1131, Aug. 1996.
19. M. Konda, T. Shibata, and T. Ohmi, "Neuron-MOS correlator based on Manhattan distance computation for event recognition hardware," 1996 IEEE International Symposium on Circuit and Systems (ISCAS 96), vol. 4, pp. 217-220, Atlanta, May 1996.
20. Y. Yamashita, T. Shibata, and T. Ohmi, "Write/verify free analog non-volatile memory using a neuron-MOS comparator," 1996 IEEE International Symposium on Circuit and Systems (ISCAS 96), vol. 4, pp. 229-232, Atlanta, May 1996.
21. A. Rita, T. Yamashita, T. Shibata, and T. Ohmi, "Neuron-MOS multiple-valued memory tech-nology for intelligent data processing," ISSCC Dig. Technical Papers, FA 16.3, pp. 270-271, Feb. 1994.
22. M. Konda, T. Shibata, and T. Ohmi, "A compact memory-merged vector-matching circuitry for neuron-MOS associative processor," IEICE Trans. Electron., vol.E82-C, no.9, pp. 1715-1721, Sept. 1999.
23. M. Ogawa and T. Shibata, "NMOS-based Gaussian-element-matching analog associative memory," Proc. 27th European Solid-State Circuits Conference (ESSCIRC 2001), ed. F. Dielacher and H. Grunbacher, pp. 272-275 (Frontier Group), Villach, Austria, Sept. 2001.
24. T. Yamasaki, A. Suzuki, D. Kobayashi, and T. Shibata, "A fast self-convergent flash-memory pro-gramming schme for MV and analog data storage," Proc. 2001 IEEE International Symposium on Circuits and Systems (ISCAS 2001), pp. IV-930-933, Sydney, Austlaria, May 2001.
25. A. Gersho, and R.M. Gray, Vector quantization and signal compression, Kluwer Academic Publishers, Boston, 1992.
26. T. Shibata, A. Nakada, M. Konda, T. Morimoto, T. Ohmi, H. Akutsu, A. Kawamura, and K. Marumoto, "A fully-parallel vector quantization processor for real-time motion picture compression," ISSCC Dig. Tech. Papers, pp. 236-237, Feb. 1997.
27. A. Nakada, T. Shibata, M. Konda, T. Morimoto, and T. Ohmi, "A fully-parallel vector quantization processor for real-time motion picture compression," IEEE J. Solid-State Circuits, vol.34, no.6, pp.822-830, June 1999.
28. A. Nakada, M. Konda, T. Morimoto, T. Yonezawa, T. Shibata, and T. Ohmi, "Fully-parallel VLSI implementation of vector quantization processor uisng neuron-MOS technology," IEICE Trans. Electron., vol.E82-C, no.9, pp. 1730-1737, Sept. 1999.
29. T. Nakai, T. Shibata, and T. Ohmi, "Neuron-MOS quasi-two-dimensional image processor for real-time motion vector detection," Proc. 4th International Conference on Soft Computing, Methodologies for the Conception, Design, and Application of Intelligent Systems, pp. 833-836, World Scientific, Singapore, 1996.
30. T. Nakai, T. Shibata, T. Yamashita, and T. Ohmi, "Neuron-MOS parallel search hardware for real-time signal processing," Analog Integrated Circuits and Signal Processing, vol.21, no.2, pp. 173-191, Nov. 1999.
31. H. Kimura and T. Shibata, "A hardware-friendly algorithm for motion-based saliency detection," the 6th International Conference on Soft computing (IIZUKA 2000), Iizuka, Japan, Oct. 2000.
32. A. Okada and T. Shibata, "A neuron-MOS parallel associator for high-speed CDMA matched filter," The 1999 IEEE International Symposium on Circuits and Systems (ISCAS '99), vol.2, pp. II-392-395, Orlando, Florida, May 30-June 2 1999,
33. M. Yagi, M. Adachi, and T. Shibata, "A hardware-friendly soft-computing algorithm for image recognition," Proc. X European Signal Processing Conference, (EUSIPCO 2000), Tampere, Finland, pp. 729-732, Sept. 4-8, 2000.
34. S. Parthasarathy, S.T. Nugent, P.G. Gregson, and D.F. Fay, "Automatic Landmarking of Cephalograms," Computers and Biomedical Research, vol.22, pp. 248-269, 1989.
35. D.J. Rudolph, J.M. Coggins, and H. Moon, "Investigation of filter sets for supervised pixel classi-fication of cephalometric landmarks by spatial spectroscopy," International J. Medical Informatics, vol.47, pp. 182-191, 1997.
36. S.P. Lloyd, "Least squares quantization in PCM," IEEE Trans. Inf. Theory, vol.IT-28, no.2, pp. 129-137, March 1982.
37. K. Zeger and A. Gersho, "A stochastic relaxation algorithm for improved vector quantiser design," Electron. Lett., no.25, pp. 896-898, July 1989.
38. T. Shibata, M. Yagi, and M. Adachi, "Soft-computing integrated circuits for intelligent information processing," Proc. Second International Conference on Information Fusion, vol.1, pp. 648-656, Sunnyvale, California, July 1999.
39. T. Yamasaki and T. Shibata, "An analog similarity evaluation circuit featuring variable functional forms," Proc. 2001 IEEE International Symposium on Circuits and Systems (ISCAS 2001), pp. III-561-564, Sydney, Australia, May 2001.
40. T. Yamasaki, K. Yamamoto, and T. Shibata, "Analog pattern classifier with flexible matching circuitry based on principal-axis-projection vector representation," Proc. 27th European Solid-State Circuits Conference (ESSCIRC 2001), ed. F. Dielacher and H. Grunbacher, pp. 212-215 (Frontier Group), Villach, Austria, Sept. 2001.
41. M. Adachi and T. Shibata, "Image representation algorithm featuring human perception of similarity for hardware recognition systems," Proc. International Conference on Artificial Intelligence (IC-AI'2001), ed. H.R. Arabnia, vol.I, 229-234 (CSREA Press, ISDBN: 1-892512-78-5), Las Vegas, Nevada, USA, June 2001.
42. T. Yamasaki and T. Shibata, "An analog soft-pattern-matching classifier and its application to overlapping pattern separation," presented at Neural Information Processing Systems (NIPS), Vancouver, Canada, Dec. 2001.
43. M. Yagi and T. Shibata, Unpublished.