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Volumn E82-C, Issue 9, 1999, Pages 1715-1720

A compact memory-merged vector-matching circuitry for neuron-MOS associative processor

Author keywords

Absolute value of difference; Associative processor; Boot strap effect; Manhattan distance; MOS

Indexed keywords

CAPACITANCE; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; INTEGRATED CIRCUIT MANUFACTURE; MOSFET DEVICES; PROM; VECTORS;

EID: 0033350398     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (2)

References (13)
  • 4
    • 85153935542 scopus 로고    scopus 로고
    • A change-based CMOS parallel analog vector quantizer
    • The MIT Press Cambridge, Massachusetts London, England
    • G. Cauwenberghs and V. Pedroni, "A change-based CMOS parallel analog vector quantizer," in NEURAL INFORMATION PROCESSING SYSTEMS 7, pp.779-786, The MIT Press Cambridge, Massachusetts London, England.
    • Neural Information Processing Systems , vol.7 , pp. 779-786
    • Cauwenberghs, G.1    Pedroni, V.2
  • 7
    • 0029696340 scopus 로고    scopus 로고
    • Neuron-MOS correlator based on manhattan distance computation for event recognition hardware
    • Atlanta, May
    • M. Konda, T. Shibata, and T. Ohmi, "Neuron-MOS correlator based on manhattan distance computation for event recognition hardware," 1996 IEEE International Symposium on Circuit and Systems (ISCAS96), vol.4, Atlanta, pp.217-220, May 1996.
    • (1996) 1996 IEEE International Symposium on Circuit and Systems (ISCAS96) , vol.4 , pp. 217-220
    • Konda, M.1    Shibata, T.2    Ohmi, T.3
  • 8
    • 27944492851 scopus 로고
    • A functional MOS transistor featuring gate-level weight sum and threshold operations
    • T. Shibata and T. Ohmi, "A functional MOS transistor featuring gate-level weight sum and threshold operations," IEEE Trans. Electron Devices, vol.39, no.6, pp. 1444-1455, 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , Issue.6 , pp. 1444-1455
    • Shibata, T.1    Ohmi, T.2
  • 10
    • 85027116681 scopus 로고
    • Neuron-MOS winner-take-all circuit and its application to associative memory
    • FA15.2
    • T. Yamashita, T. Shibata, and T. Ohmi, "Neuron-MOS winner-take-all circuit and its application to associative memory," ISSCC Dig. of Technical Papers, FA15.2, pp.236-237, 1993.
    • (1993) ISSCC Dig. of Technical Papers , pp. 236-237
    • Yamashita, T.1    Shibata, T.2    Ohmi, T.3
  • 11
    • 0029359665 scopus 로고
    • Neuron-MOS neural network using self-learning-compatible synapse circuits
    • Aug.
    • T. Shibata, H. Kosaka, H. Ishii, and T. Ohmi, "Neuron-MOS neural network using self-learning-compatible synapse circuits," IEEE J. Solid-State Circuits, vol.30, no.8, Aug. 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , Issue.8
    • Shibata, T.1    Kosaka, H.2    Ishii, H.3    Ohmi, T.4
  • 12
    • 0028098461 scopus 로고
    • Neuron MOS multiple-valued memory technology for intelligent data processing
    • FA16.3
    • R. Au, T. Yamashita, T. Shibata, and T. Ohmi, "Neuron MOS multiple-valued memory technology for intelligent data processing," ISSCC Dig. of Technical Papers, FA16.3, pp.270-271, 1994.
    • (1994) ISSCC Dig. of Technical Papers , pp. 270-271
    • Au, R.1    Yamashita, T.2    Shibata, T.3    Ohmi, T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.