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1
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0002797572
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A memory-based parallel processor for vector quantization
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Sept.
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K. Kobayashi, M. Kinoshita, M. Takeuchi, H. Onodera, and K. Tamaru, "A memory-based parallel processor for vector quantization," 22nd European Solid-State Circuits Conference, pp.184-187, Sept. 1996.
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(1996)
22nd European Solid-state Circuits Conference
, pp. 184-187
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-
Kobayashi, K.1
Kinoshita, M.2
Takeuchi, M.3
Onodera, H.4
Tamaru, K.5
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2
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0031069458
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A fully-parallel vector quantization processor for real-time motion picture compression
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FP16.9
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T. Shibata, T. Nakada, M. Konda, T. Morimoto, T. Ohmi, H. Akutsu, A. Kawamura, and K. Marumoto, "A fully-parallel vector quantization processor for real-time motion picture compression," ISSCC Dig. of Technical Papers, FP16.9, pp.270-271, 1997.
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(1997)
ISSCC Dig. of Technical Papers
, pp. 270-271
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-
Shibata, T.1
Nakada, T.2
Konda, M.3
Morimoto, T.4
Ohmi, T.5
Akutsu, H.6
Kawamura, A.7
Marumoto, K.8
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3
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84954252347
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An 8 bit CMOS vector A/D converter
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WP2.7
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G. Tyson Tuttle, S. Fallahi, and A.A. Abidi, "An 8 bit CMOS vector A/D converter," ISSCC Dig. of Technical Papers, WP2.7, pp.38-39, 1993.
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(1993)
ISSCC Dig. of Technical Papers
, pp. 38-39
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-
Tyson Tuttle, G.1
Fallahi, S.2
Abidi, A.A.3
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4
-
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85153935542
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A change-based CMOS parallel analog vector quantizer
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The MIT Press Cambridge, Massachusetts London, England
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G. Cauwenberghs and V. Pedroni, "A change-based CMOS parallel analog vector quantizer," in NEURAL INFORMATION PROCESSING SYSTEMS 7, pp.779-786, The MIT Press Cambridge, Massachusetts London, England.
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Neural Information Processing Systems
, vol.7
, pp. 779-786
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-
Cauwenberghs, G.1
Pedroni, V.2
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5
-
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0030081934
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Advances in neuron-MOS applications
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T. Shibata, T. Nakai, N.M. Yu, Y. Yamashita, M. Konda, and T. Ohmi, "Advances in neuron-MOS applications," ISSCC Dig. of Technical Papers, pp.304-305, 1996.
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(1996)
ISSCC Dig. of Technical Papers
, pp. 304-305
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-
Shibata, T.1
Nakai, T.2
Yu, N.M.3
Yamashita, Y.4
Konda, M.5
Ohmi, T.6
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6
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6744234390
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Neuron-MOS-based association hardware for real-time event recognition
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Lausanne, Feb.
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T. Shibata, M. Konda, Y. Yamashita, T. Nakai, and T. Ohmi, "Neuron-MOS-based association hardware for real-time event recognition," Proc. Fifth International Conference on Microelectronics for Neural Networks and Fuzzy Systems (MicroNeuro '96), pp.94-101, Lausanne, Feb. 1996.
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(1996)
Proc. Fifth International Conference on Microelectronics for Neural Networks and Fuzzy Systems (MicroNeuro '96)
, pp. 94-101
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-
Shibata, T.1
Konda, M.2
Yamashita, Y.3
Nakai, T.4
Ohmi, T.5
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7
-
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0029696340
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Neuron-MOS correlator based on manhattan distance computation for event recognition hardware
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Atlanta, May
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M. Konda, T. Shibata, and T. Ohmi, "Neuron-MOS correlator based on manhattan distance computation for event recognition hardware," 1996 IEEE International Symposium on Circuit and Systems (ISCAS96), vol.4, Atlanta, pp.217-220, May 1996.
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(1996)
1996 IEEE International Symposium on Circuit and Systems (ISCAS96)
, vol.4
, pp. 217-220
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Konda, M.1
Shibata, T.2
Ohmi, T.3
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8
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27944492851
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A functional MOS transistor featuring gate-level weight sum and threshold operations
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T. Shibata and T. Ohmi, "A functional MOS transistor featuring gate-level weight sum and threshold operations," IEEE Trans. Electron Devices, vol.39, no.6, pp. 1444-1455, 1992.
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(1992)
IEEE Trans. Electron Devices
, vol.39
, Issue.6
, pp. 1444-1455
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-
Shibata, T.1
Ohmi, T.2
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9
-
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0029707651
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Write/Verify free analog non-volatile memory using neuron-MOS comparator
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Atlanta, May
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Y. Yamashita, T. Shibata, and T. Ohmi, "Write/Verify free analog non-volatile memory using neuron-MOS comparator," 1996 IEEE International Symposium on Circuit and Systems (ISCAS96), vol.4, Atlanta, pp.229-232, May 1996.
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(1996)
1996 IEEE International Symposium on Circuit and Systems (ISCAS96)
, vol.4
, pp. 229-232
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-
Yamashita, Y.1
Shibata, T.2
Ohmi, T.3
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10
-
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85027116681
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Neuron-MOS winner-take-all circuit and its application to associative memory
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FA15.2
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T. Yamashita, T. Shibata, and T. Ohmi, "Neuron-MOS winner-take-all circuit and its application to associative memory," ISSCC Dig. of Technical Papers, FA15.2, pp.236-237, 1993.
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(1993)
ISSCC Dig. of Technical Papers
, pp. 236-237
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-
Yamashita, T.1
Shibata, T.2
Ohmi, T.3
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11
-
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0029359665
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Neuron-MOS neural network using self-learning-compatible synapse circuits
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Aug.
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T. Shibata, H. Kosaka, H. Ishii, and T. Ohmi, "Neuron-MOS neural network using self-learning-compatible synapse circuits," IEEE J. Solid-State Circuits, vol.30, no.8, Aug. 1995.
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(1995)
IEEE J. Solid-State Circuits
, vol.30
, Issue.8
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-
Shibata, T.1
Kosaka, H.2
Ishii, H.3
Ohmi, T.4
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12
-
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0028098461
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Neuron MOS multiple-valued memory technology for intelligent data processing
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FA16.3
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R. Au, T. Yamashita, T. Shibata, and T. Ohmi, "Neuron MOS multiple-valued memory technology for intelligent data processing," ISSCC Dig. of Technical Papers, FA16.3, pp.270-271, 1994.
-
(1994)
ISSCC Dig. of Technical Papers
, pp. 270-271
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Au, R.1
Yamashita, T.2
Shibata, T.3
Ohmi, T.4
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