Neuron-MOS parallel search hardware for real-time signal processing

Analog Integrated Circuits and Signal Processing

Volumn 21, Issue 2, 1999, Pages 173-191

  Nakai, Tsutomu ^a,c   Yamashita, Takeo ^a,e   Ohmi, Tadahiro ^a   Shibata, Tadashi ^b,d  

^a TOHOKU UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c FUJITSU LABORATORIES LTD   (Japan)

^d OSAKA UNIVERSITY   (Japan)

^e HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BINARY CODES; COMPUTER HARDWARE; COMPUTER SIMULATION; IMAGE PROCESSING; INTEGRATED CIRCUIT MANUFACTURE; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; SIGNAL PROCESSING; SORTING;

DATA SORTING CIRCUIT; MOTION VECTOR DETECTOR; NEURON MOS;

MOSFET DEVICES;

EID: 0033225717     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008325908450     Document Type: Article

References (9)

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8. T. Shibata and T. Ohmi, "Neuron MOS binary-logic integrated circuits - Part II : Simplifying techniques of circuit configuration and their practical applications." IEEE Trans. Electron Devices 40(5), pp. 974-979, 1993.
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