Design considerations for CMOS near the limits of scaling

Solid-State Electronics

Volumn 46, Issue 3, 2002, Pages 315-320

  Frank, David J ^a   Taur, Yuan ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

CMOS; MOSFET design; Power dissipation; Scaling limits; Tunneling currents

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC INSULATORS; ENERGY DISSIPATION; MOSFET DEVICES; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; THRESHOLD VOLTAGE;

SCALING LIMITS; TUNNELING CURRENTS;

CMOS INTEGRATED CIRCUITS;

EID: 0036498483     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(01)00102-2     Document Type: Article

References (11)

1. Future prospects for Si CMOS technology
2. 25 nm CMOS design considerations
3. Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide MOSFETs
4. Supply and threshold voltage optimization for low power design
5. Reliability projection for ultra-thin oxides at low voltage
6. Monte Carlo modeling of threshold variation due to dopant fluctuations
7. Generalized scale length for two-dimensional effects in MOSFETs
8. Design considerations for CMOS near the limits of scaling