On-line testing of multi-source noise-induced errors on the interconnects and buses of system-on-chips

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 491-499

  Zhao, Yi ^a   Chen, Li ^a   Dey, Sujit ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

DEEP SUBMICRON NOISE EFFECTS; MULTI SOURCE NOISE EFFECTS; ONLINE TESTING; SYSTEM ON CHIPS;

INTEGRATED CIRCUIT TESTING;

EID: 0036446518     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2002.1041799     Document Type: Article

References (21)

1. D. Sylvester and K. Keutzer, A Global Wiring Paradigm for Deep Submicron Design, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, vol. 19, No.2, pp.242-252, 2000.
2. L. Pileggi, Coping with RC(L) Interconnect Design Headaches, Proceedings of 1995 IEEE/ACM International Conference on Computer-Aided Design, pp. 246-252, 1995.
3. M. A. Breuer and S. K. Gupta, Process Aggravated Noise (PAN): New Validation and Test Problems, Proceedings of 1996 International Test Conference, pp. 914-923, 1996.
4. A. Deutsch, G. Kopcsay, P. Restle, H. Smith, G. Katopis, W. Becker, P. Coteus, C. Surovic, B. Rubin, R. Dunne, T. Gallo, K. Jenkins, L. Terman, R. Dennard, G. Sai-Halasz, B. Krauter, and D. Knebel, When are Transmission-Line Effects Important for On-Chip Interconnections?, IEEE Transactions on Microwave Theory and Techniques, Vol. 45, No. 10, pp. 1836-1846, 1997.
5. P. Nordholz, D. Treytnar, J. Otterstedt, H. Grabinski, D. Niggermeyer, and T.W. Williams, Signal Integrity Problems in Deep Submicron arising from Interconnects between Cores, Proceedings of IEEE VLSI Test Symposium, pp. 28-33, 1998.
6. W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.
7. C. Metra, M. Favalli, B. Ricco, Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines, IEEE Transactions on Computers, vol.49, (no.6), pp. 560-74, June 2000.
8. M. Nicolaidis, Time redundancy based soft-error tolerance to rescue nanometer technologies, Proceedings 17th IEEE VLSI Test Symposium, pp. 89-94, 1999.
9. J. Gambles, K. J. Hass, US Patent 6326809, 1999.
10. Y. I. Ismail, E. G. Friedman, and J. L. Neves, Figures of merit to characterize the importance of on-chip inductance, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.7, (no.4), pp.442-449, 1999.
11. K. T. Lee, C. Nordquist, and J. A. Abraham, Automatic Test Generation for Crosstalk Glitches in Digital Circuits, Proceedings of 16th IEEE VLSI Test Symposium, pp. 34-39, 1998.
12. W. Chen, S. K. Gupta, and M. A. Breuer, Test Generation in VLSI Circuits for Crosstalk Noise, Proceedings of IEEE International Test Conference, pp. 641-650, 1998.
13. M. Cuviello, S. Dey, X. Bai and Y. Zhao, Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects, Proceedings of 1999 IEEE/ACM International Conference on Computer-Aided Design, pp. 297-303, 1999.
14. Y. Jiang, T. Young, and K. T. Cheng, VIP- An input Pattern Generator for Identifying Critical Voltage Drop for Deep Sub-micron Designs, Proceedings of 1999 International Symposium on Low Power Electronics and Design, pp.156-161, 1999.
15. National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1999.
16. Signal integrity/physical verification products of Simplex (ElectronStrom™ etc.) at company website: http : //www.simplex. com/ img/ electron-storm.pdf.
17. Signal integrity/physical verification products of Cadence Corporation, company website: http: // www.cadence.com/products/ sidigital .html.
18. L. Anghel and M. Nicolaidis, Cost reduction and evaluation of a temporary faults detecting technique Proceedings of Design, Automation and Test in Europe Conference and Exhibition 2000, p.591-8, 2000.
19. R. Rajsuman, System-on-a Chip: Design and Test, Artech House, p. 36, 2000.
20. Siemens AG, OMI 324 Draft Standard: PI-Bus, Rev. 0.3d, 1994.
21. Center for VLSI and Computer Graphics, University of Sussex, PI-Bus VHDL Toolkit, version 3.1, 1996.