Enhancing test efficiency for delay fault testing using multiple-clocked schemes

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 371-374

  Liou, Jing Jia ^a   Wang, Li C ^a   Cheng, Kwang Ting ^a   Dworak, Jennifer ^b   Mercer, M Ray ^b   Kapur, Rohit ^c   Williams, Thomas W ^c  

^a University of California   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

^c SYNOPSYS INC   (United States)

Author keywords

Delay testing; Statistical timing analysis; Transition fault model

Indexed keywords

STATISTICAL TIMING ANALYSIS;

COMPUTER SIMULATION; FAULT TOLERANT COMPUTER SYSTEMS; PROBABILITY DISTRIBUTIONS; SPURIOUS SIGNAL NOISE; STATISTICAL METHODS;

DELAY CIRCUITS;

EID: 0036058621     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012652     Document Type: Article

References (11)

1. Defect-based delay testing of resistive vias-contacts, a critical evaluation
2. New validation and test problems for high performance deep sub-micron VLSI circuits
3. Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis
4. Performance sensitivity analysis using statistical methods and its applications to delay testing
5. A variable observation time method for testing dlay faults
6. Optimized test application timing for AC test
7. Effectiveness of a variable sampling time strategy for delay fault diagnosis
8. Delay fault coverage enhancement using variable observation times
9. Analysis of tuning failures due to random AC defects in VLSI moduels