Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine

SIGPLAN Notices (ACM Special Interest Group on Programming Languages)

Volumn 33, Issue 11, 1998, Pages 46-57

  Lee, Walter ^a   Barua, Rajeev ^a   Frank, Matthew ^a   Srikrishna, Devabhaktuni ^a   Babb, Jonathan ^a   Sarkar, Vivek ^a   Amarasinghe, Saman ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0346339908     PISSN: 03621340     EISSN: None     Source Type: Journal    
DOI: 10.1145/291006.291018     Document Type: Article

References (26)

1. I. Ahmad, Y. Kwok, and M. Wu. Analysis, Evaluation, and Comparison of Algorithms for Scheduling Task Graphs on Parallel Processors. In Proceedings of the Second International Symposium on Parallel Architectures, Algorithms, and Networks, pages 207-213, June 1996.
2. S. Amarasingle, J. Anderson, C. Wilson, S. Liao, B. Murphy, R. French, and M. Lam. Multiprocessors from a Software Perspective. IEEE Micro, pages 52-61, June 1996.
3. D. August, W. Hwu, and S. Mahlke. A Framework for Balancing Control Flow and Predication. In Proceedings of the 30th International Symposium on Microarchitecture, Dec. 1997.
4. J. Babb, M. Frank, V. Lee, E. Waingold, R. Barua, M. Taylor, J. Kim, S. Devabhaktuni, and A. Agarwal. The RAW Benchmark Suite: Computation Structures for General Purpose Computing. In IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, Apr. 1997.
5. J. Babb, R. Tessier, M. Dahl, S. Hanono, D. Hoki, and A. Agarwal. Logic emulation with virtual wires. IEEE Transactions on Computer Aided Design, 16(6):609-626, June 1997.
6. S. Banerjia. Instruction Scheduling and Fetch Mechanism for Clustered VLIW Processors. In Ph.D Thesis, North Carolina State University, 1998.
7. R. Barua, W. Lee, S. Amarasinghe, and A. Agarwal. Maps: A Compiler-Managed Memory System for Raw Machines. Technical Memo TM-583, MIT LCS, July 1998.
8. R. Barua, W. Lee, S. Amarasinghe, and A. Agarwal. Memory Bank Disambiguation using Modulo Unrolling for Raw Machines. In Proceedings of the ACM/IEEE Fifth Int'l Conference on High Performance Computing(HIPC), Dec. 1998.
9. A. Capitanio, N. Dutt, and A. Nicolau. Partitioned Register Files for VLIWs: A Preliminary Analysis of Tradeoffs. In Proceedings of the 25th International Symposium on Microarchitecture, Dec. 1992.
10. G. Desoli. Instruction Assignment for Clustered VLIW DSP Compilers: A New Approach. Technical report, HP HPL-98-13, Feb. 1998.
11. M. Dikaiakos, A. Rogers, and K. Steiglitz. A Comparison of Techniques Used for Mapping Parallel Algorithms to Message-Passing Multiprocessors. In Proceedings of the 6th IEEE Symposium on Parallel and Distributed Processing, Oct. 1994.
12. J. R. Ellis. Bulldog: A Compiler for VLIW Architectures. In Ph.D Thesis, Yale University, 1985.
13. J. A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions on Computers, 7(C-30):478-490, July 1981.
14. L. Gwennap. Digital 21264 Sets New Standard. Microprocessor Report, pages 11-16, Oct. 1996.
15. W. Hwu, S. Mahlke, W. Chen, P. Chang, N. Warter, R. Bringmann, R. Ouellette, R. Hank, T. Kiyohara, G. Haab, J. Holm, and D. Lavery. The Superblock: An Effective Technique for VLIW and Superscalar Compilation. The Journal of Supercomputing, 7(1), Jan. 1993.
16. V. Kathail, M. Schlansker, and B. R. Rau. HPL PlayDoh Architecture Specification: Version 1.0. Technical report, HP HPL-93-80, Feb. 1994.
17. M. S. Lam. Software Pipelining: An Effective Scheduling Technique for VLIW Machines. In Proc. Int'l Conf. on Programming Language Design and Implementation (PLDI), pages 318-328, June 1988.
18. M. S. Lam and R. P. Wilson. Limits of Control Flow on Parallelism. In Proceedings of 19th Annual International Symposium on Computer Architecture, pages 46-57, May 1992.
19. P. Lowney, S. Freudenberger, T. Karzes, W. Lichtenstein, R. Nix, J. O'Donnell, and J. Ruttenberg. The Multiflow Trace Scheduling Compiler. In Journal of Supercomputing, pages 51-142, Jan. 1993.
20. V. Sarkar. Partitioning and Scheduling Parallel Programs for Multiprocessors. Pitman, London and The MIT Press, Cambridge, Massachusetts, 1989. In the series, Research Monographs in Parallel and Distributed Computing.
21. M. D. Smith. Extending SUIF for Machine-dependent Optimizations. In Proceedings of the First SUIF Compiler Workshop, pages 14-25, Stanford, CA, Jan. 1996.
22. G. Sohi, S. Breach, and T. Vijaykumar. Multiscalar Processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 414-425, 1995.
23. E. Waingold, M. Taylor, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, S. Devabhaktuni, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal. Baring It All To Software: Raw Machines. Computer, pages 86-93, Sept. 1997.
24. R. Wilson, R. French, C. Wilson, S. Amarasinghe, J. Anderson, S. Tjiang, S. Liao, C.-W. Tseng, M. Hall, M. Lam, and J. Hennessy. SUIF: An Infrastructure for Research on Parallelizing and Optimizing Compilers. ACM SIGPLAN Notices, 29(12), Dec. 1996.
25. T. Yang and A. Gerasoulis. List Scheduling With and Without Communication. Parallel Computing Journal, 19:1321-1344, 1993.
26. T. Yang and A. Gerasoulis. DSC: Scheduling Parallel Tasks on an Unbounded Number of Processors. IEEE Transactions on Parallel and Distributed Systems, 5(9):951-967, 1994.