A novel approach to random pattern testing of sequential circuits

IEEE Transactions on Computers

Volumn 47, Issue 1, 1998, Pages 129-134

  Nachman, Lama ^a   Saluja, Kewal K ^b,d   Upadhyaya, S J ^c,d   Reuse, Robert ^c  

^a INTEL CORPORATION   (United States)

^b University of Wisconsin Madison   (United States)

^c UNIVERSITY AT BUFFALO   (United States)

^d IEEE

Author keywords

Fault coverage; Hold method; Partial scan; Random pattern testing; Sequential circuit testing

Indexed keywords

ELECTRIC NETWORK ANALYSIS; RANDOM PROCESSES;

FAULT COVERAGE; PARTIAL SCAN; RANDOM PATTERN TESTING; SEQUENTIAL CIRCUIT TESTING;

SEQUENTIAL CIRCUITS;

EID: 0031699610     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.656097     Document Type: Article

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