Timed pattern generation for noise-on-delay calculation

Proceedings-Design Automation Conference

Volumn , Issue , 2002, Pages 870-873

  Choi, Seung Hoon ^a   Dartu, Florentin ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

STATIC TIMING ANALYSIS (STA);

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SIMULATION; CONVERGENCE OF NUMERICAL METHODS; CROSSTALK; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE;

DELAY CIRCUITS;

EID: 0036044499     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012744     Document Type: Article

References (13)

1. Interconnect scaling-the real limiter to high performance ULSI
2. Dynamic noise analysis for precharge-evaluate logic family
3. Harmony: Static noise analysis of deep submicron digital integrated circuits
4. A new gate delay model for simultaneous switching and its applications
5. Timing verification and timing analysis program
6. Miller factor for gate-level coupling delay calculation
7. On switch factor based analysis of coupled RC interconnects
8. Switching window computation for static timing analysis in presence of crosstalk noise
9. TACO: Timing analysis with coupling
10. Calculating worst-case gate delays due to dominant capacitance coupling
11. Determination of worst-case aggressor alignment for delay calculation
12. Driver modeling and alignment for worst-case delay noise