Switch-level delay test

IEEE International Test Conference (TC)

Volumn , Issue , 1999, Pages 171-180

  Natarajan, Suriyaprakash ^a   Gupta, Sandeep K ^a   Breuer, Melvin A ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC DELAY LINES; ELECTRIC NETWORK ANALYSIS; LOGIC CIRCUITS; LOGIC GATES; SWITCHING CIRCUITS; SWITCHING THEORY;

FUNCTIONAL SENSITIZATION; GATE LEVEL MODELS; ROBUST PATH DELAY TEST; SWITCH LEVEL DELAY TEST;

INTEGRATED CIRCUIT TESTING;

EID: 0033326428     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)