Fast algorithm for locating and correcting simple design errors in VLSI digital circuits

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1997, Pages 45-50

  Veneris, Andreas G ^a   Hajj, Ibrahim N ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ERROR CORRECTION; ERROR DETECTION; LOGIC GATES; MODIFICATION; VECTORS; VLSI CIRCUITS;

DESIGN ERROR DETECTION AND CORRECTION; DESIGN ERRORS; TEST VECTOR SIMULATION;

COMPUTER AIDED LOGIC DESIGN;

EID: 0030704410     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)