Multiple design error diagnosis and correction in digital VLSI circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 58-63

  Veneris, Andreas ^a   Venkataraman, Srikanth ^a   Hajj, Ibrahim N ^a   Fuchs, W Kent ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; ERROR CORRECTION; ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; VECTORS;

CPU TIME; MULTIPLE DESIGN ERROR DIAGNOSIS AND CORRECTION; TEST VECTOR SIMULATION;

VLSI CIRCUITS;

EID: 0032670489     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (15)