메뉴 건너뛰기





Volumn 8, Issue 2, 1996, Pages 113-127

Method for automatic design error location and correction in combinational logic circuits

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BACKPROPAGATION; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; ERROR CORRECTION; ERROR DETECTION; LOGIC GATES;

EID: 0030121399     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF02341818     Document Type: Article
Times cited : (12)

References (20)
  • Reference 정보가 존재하지 않습니다.

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.