Clock-gating and its application to low power design of sequential circuits

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1997, Pages 479-482

  Wu, Qing ^a   Pedram, Massoud ^a   Wu, Xunwei ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC LOSSES; FLIP FLOP CIRCUITS; LOGIC DESIGN; LOGIC GATES; TIMING CIRCUITS;

CLOCK GATING METHOD;

SEQUENTIAL CIRCUITS;

EID: 0030650150     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)