A 2.4Gb/s/pin simultaneous bidirectional parallel link with per pin skew compensation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 256-257

  Yeung, E ^a   Horowitz, M ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; CURVE FITTING; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE;

BIDIRECTIONAL SIGNALING;

TRANSCEIVERS;

EID: 0034428362     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A 900Mb/s bidirectional signalling scheme
2. A CMOS gate array with 600Mb/s simultaneous bidirectional I/O circuits
3. A 700Mb/s/pin CMOS signalling interface using current integrating receivers
4. A semi-digital delay locked loop with unlimited phase shift capability and 0.08-400Mhz operating range
5. Low-Jitter process-independent DLL and PLL based on self-biased techniques
6. Applications of on-chip samplers for test and measurement of integrated circuits