5Gb/s bidirectional balanced-line link compliant with plesiochronous clocking

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 64-65+431

  Tamura, H ^a   Kibune, M ^a   Takahashi, Y ^a   Doi, Y ^a   Chiba, T ^a   Higashi, H ^a   Takauchi, H ^a   Ishida, H ^a   Gotoh, K ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; DIGITAL FILTERS; DIGITAL SIGNAL PROCESSING; DIGITAL TO ANALOG CONVERSION; ELECTRIC CLOCKS; ELECTRONIC EQUIPMENT MANUFACTURE; PHASE LOCKED LOOPS; SWITCHING CIRCUITS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS; VOLTAGE REGULATORS;

PHASE-TO-DIGITAL CONVERTERS (PDC); SWITCHED CAPACITORS (SC);

TELECOMMUNICATION LINKS;

EID: 0035061179     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A semidigital dual delay-locked loop
2. A 90mW 4Gb/s equalized I/O circuit with input offset cancellation
3. Low-jitter processes-independent DLL and PLL based on self-biased techniques