Numerical confirmation of inelastic trap-assisted tunneling (ITAT) as SILC mechanism

IEEE Transactions on Electron Devices

Volumn 48, Issue 10, 2001, Pages 2317-2322

  Kang, Ting Kuo ^b   Chen, Ming Jer ^a,b   Liu, Chuan Hsi ^c   Chang, Yih J ^c   Fan, Shou Kong ^c  

^a IEEE

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

Flash; Gated diode; Inelastic tunneling; MOSFET; Oxide breakdown; Percolation; SILC; Stress induced leakage current; Trap assisted tunneling

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENT MEASUREMENT; ELECTRON TRAPS; ELECTRON TUNNELING; HOLE TRAPS; LEAKAGE CURRENTS; MATHEMATICAL MODELS; MOSFET DEVICES; NUMERICAL METHODS; VOLTAGE MEASUREMENT;

CHARGE-TO-BREAKDOWN STATISTICS; INELASTIC TRAP ASSISTED TUNNELING; NEUTRAL ELECTRON TRAP DENSITY; STRESS INDUCED LEAKAGE CURRENT; TUNNELING PROBABILITY; TUNNELING RELAXATION TIME;

SEMICONDUCTOR DEVICE TESTING;

EID: 0035472026     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.954471     Document Type: Article

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