Physical performance limits for shared buffer ATM switches

IEEE Transactions on Communications

Volumn 45, Issue 8, 1997, Pages 997-1007

  Schultz, Kenneth J ^a   Glenn Gulak, P ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Aggregate throughput; Atm switches; Physical performance; Power dissipation; Shared buffer; VLSI

Indexed keywords

BUFFER CIRCUITS; CHANNEL CAPACITY; ELECTRIC NETWORK ANALYSIS; ENERGY DISSIPATION; MICROPROCESSOR CHIPS; PACKET SWITCHING; TELECOMMUNICATION TRAFFIC; VLSI CIRCUITS;

AGGREGATE THROUGHPUT; BUFFER CAPACITY;

ASYNCHRONOUS TRANSFER MODE;

EID: 0031209798     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/26.618317     Document Type: Article

References (30)

1. H. Komiya, "Future technological and economic prospects for VLSI," in IEEE ISSCC Dig. Tech. Papers, 1993, pp. 16-19.
2. H. Ahmadi and W. E. Denzel, "A survey of modern high-performance switching techniques," IEEE J. Select. Areas Commun., vol. 7, pp. 1091-1103, Sept. 1989.
3. M. Mizukami, Y. Satoh, Y. Nakano, T. Kozaki, Y. Mikami, T. Kanno, and Y. Sakurai, "CMOS circuit technologies for digital communication systems," in Proc. 14th Int. Switching Symp., 1992, pp. 251-255.
4. P. Coppo, M. D'Ambrosio, and R. Melen, "Optimal cost/performance design of ATM switches," in Proc. IEEE INFOCOM, 1992, pp. 446-458.
5. E. W. Zegura, "Architectures for ATM switching systems," IEEE Commun. Mag., pp. 28-37, Feb. 1993.
6. J.-L. Lardy, "Estimation des performances des circuits integres: Application a la commutation ATM," Ann. Telecommun., vol. 48, pp. 181-195, Mar.-Apr. 1993.
7. K. J. Schultz and P. G. Gulak, "Physical performance limits for shared buffer ATM switches to the year 2005," in Proc. 15th Int. Switching Symp., vol. 1, 1995, pp. 294-298.
8. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
9. M. G. Hluchyj and M. R. Karol, "Queueing in high-performance packet switching," IEEE J. Select. Areas Commun., vol. 6, pp. 1587-1597, Dec. 1988.
10. F. A. Tobagi, "Fast packet switch architectures for broadband integrated services digital networks," Proc. IEEE, vol. 78, pp. 133-167, Jan. 1990.
11. W. W. Chu, "Buffer behavior for batch poisson arrivals and single constant output," IEEE Trans. Commun., vol. 18, pp. 613-618, Oct. 1970.
12. H. Kuwahara, N. Endo, M. Ogino, and T. Kozaki, "A shared buffer memory switch for an ATM exchange," in Proc. IEEE Int. Commun. Conf., 1989, pp. 118-122.
13. T. Kozaki, N. Endo, Y. Sakurai, O. Matsubara, M. Mizukami, and K. Asano, "32 × 32 shared buffer type ATM switch VLSI's for B-ISDN's," IEEE J. Select. Areas Commun., vol. 9, pp. 1239-1247, Oct. 1991.
14. S. Tanaka, Y. Shobatake, K. Sakaue, M. Motoyama, S. Takatsuka, M. Ishibe, S. Shimizu, M. Noda, Y. Shimojoh, E. Kamagata, K. Seta, Y. Niitsu, K. Tamaura, and H. Momose, "A 400 Mb/s 8 × 8 BiCMOS ATM switch LSI with 128 kb on-chip shared memory," in IEEE ISSCC Dig. Tech. Papers, 1991, pp. 242-243.
15. L. Licciardi, S. Claretto, M. Fassino, M. Gandini, M. Turolla, and V. Vercellone, "A fully CMOS 622 Mbit/s switching element," in Proc. IEEE Custom Integrated Circuits Conf., 1992, pp. 14.2.1-14.2.4.
16. R. H. Hofmann and R. Muller, "A multifunctional high-speed switch element for ATM applications," IEEE J. Solid-State Circuits, vol. 27, pp. 1036-1040, July 1992.
17. A. Chemarin, A. Andre, A. Botta, J. Majos, J.-L. Rainard, H. Teyssier, and P. Thorel, "A high-speed CMOS circuit for 1.2-Gb/s 16 × 16 ATM switching," IEEE J. Solid-State Circuits, vol. 27, pp. 1116-1120, July 1992.
18. K. J. Schultz and P. G. Gulak, "Throttled-buffer asynchronous switch for ATM," IEICE Trans. Commun., vol. E77-B, pp. 351-358, Mar. 1994.
19. K. J. Schultz, "CAM-based circuits for ATM switching networks:," Ph.D. dissertation, Univ. Toronto, Canada, 1996.
20. H. Saito, H. Yamanaka, H. Yamada, M. Tuzuki, H. Kondoh, Y. Matsuda, and K. Oshima, "Multicast function and its LSI implementation in a shared multibuffer switch," in Proc. INFOCOM, 1994, pp. 315-322.
21. E. Munter, J. Parker, and P. Kirby, "A high capacity ATM switch based on advanced electronic and optical technologies," in Proc. 15th Int. Switching Symp., vol. 1, 1995, pp. 389-393.
22. A. R. Corless and A. D. Trigg, "Packaging considerations for flip-chip multi-chip modules," in Proc. Int. Conf. High-Performance Electron. Packaging, 1990, pp. 49-57.
23. J. D. Cressler, "Silicon-germanium heterojunction bipolar technology: The next leap in silicon?," ISSCC Dig. Tech. Papers, pp. 24-27, 1994.
24. M. J. Karol, K. Y. Eng, M. A. Pashan, R. A. Spanke, and G. D. Martin, "Hierachical gigabit ATM switching: Applications and performance," in Proc. 14th Int. Switching Symp., vol. 2, 1992, pp. 306-310.
25. E. Munter, private communication, 1995.
26. N. P. Jouppi, P. Boyle, J. Dion, M. J. Doherty, A. Eustace, R. Haddad, R. Mayo, S. Menon, L. Monier, D. Stark, S. Turrini, and L. Yang, "A 300 MHz 115 W 32 b bipolar ECL microprocessor with on-chip caches," in IEEE ISSCC Dig. Tech. Papers, 1993, pp. 84-85.
27. K. J. Schultz and P. G. Gulak, "Fully-parallel integrated CAM/RAM using preclassification to enable large capacities," IEEE J. Solid-State Circuits, vol. 31, pp. 689-699, May 1996.
28. H. Yamanaka, H. Kondoh, H. Saito, M. Tsuzuki, Y. Sasaki, S. Kohama, H. Yamada, Y. Matsuda, and K. Oshima, "A scalable nonblocking shared multibuffer ATM switch with a new concept of searchable queue," in Proc. 15th Int. Switching Symp., vol. 1, 1995, pp. 278-282.
29. K. Y. Eng, M. A. Pashan, R. A. Spanke, M. J. Karol, and G. D. Martin, "A high-performance prototype 2.5 Gb/s ATM switch for broadband applications," in Proc. IEEE GLOBECOM, 1992, pp. 111-117.
30. S. Kumar and D. P. Agrawal, "A shared buffer direct-access (SBDA) switch architecture for ATM-based networks," in Proc. IEEE Int. Commun. Conf., 1994, pp. 101-105.