Robust RTL power macromodels

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 4, 1998, Pages 578-581

  Bogliolo, Alessandro ^a   Benini, Luca ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Cell based power estimation; Logic simulation; Power consumption model; Switching activity

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; POWER CONTROL; STATISTICAL TESTS;

REGISTER-TRANSFER LEVEL POWER MODELING;

DIGITAL CIRCUITS;

EID: 0032304489     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.736131     Document Type: Article

References (15)

1. S. Powell et al., "Estimating power dissipation of VLSI signal processing chips: the PFA techniques," in Proc. Workshop VLSI Signal Processing, vol. IV, pp. 250-259, 1990.
2. H. Mehta et al., "Energy characterization based on clustering," in Proc. Design Automation Conf., 1996, pp. 702-707.
3. Q. Qiu et al., "Cycle-accurate macro-models for RT-level power analysis," in Proc. Int. Symp. Low Power Electron. Design, 1997, pp. 125-130.
4. P. Landman et al., "Architectural power analysis, the dual bit type method," IEEE Trans. VLSI Syst., vol. 3, pp. 173-187, June 1995.
5. S. Gupta et al., "Power macromodeling for high-level power estimation," in Proc. Design Automation Conf., 1997, pp. 365-370.
6. L. Benini et al., "Regression models for behavioral power estimation," Power Timing Modeling Optimization and Simulation, pp. 179-187, 1996.
7. A. Bogliolo et al., "Adaptive least mean square behavioral power modeling," in Proc. European Design and Test Conf., 1997, pp. 404-410.
8. P. McGeer et al., "Fast discrete function evaluation using decision diagrams," in Proc. Int. Conf. Computer-Aided Design, 1995, pp. 402-407.
9. R. French et al., "A general method for compiling event-driven simulations," in Proc. Design Automation Conf., 1995, pp. 151-146.
10. D. M. Lewis, "A hierarchical compiled code event-driven logic simulator," IEEE Trans. Computer-Aided Design, vol. 10, pp. 726-737, 1991.
11. Z. Wang et al., "LECSIM: A levelized event driven compiled logic simulation," in Proc. Design Automation Conf., 1990, pp. 491-496.
12. C. Scholl et al., "Functional simulation using binary decision diagrams," in Proc. Int. Conf. Computer-Aided Design, 1997, pp. 8-12.
13. A. Bogliolo et al., "Characterization-free behavioral power modeling," in Proc. Design Automation and Test Europe, 1998, pp. 767-773.
14. L. Benini et al., "Analysis of glitch power dissipation in CMOS IC's," in Proc. Int. Symp. Low Power Design, 1995, pp. 123-128.
15. S. Yang, "Logic synthesis and optimization benchmarks user guide version 3.0," Microelectron. Center of North Carolina, Research Triangle Park, NC, Tech. Rep., 1991.