SCOPUS 정보 검색 플랫폼 - 논문 보기

메뉴 건너뛰기

Microelectronics Journal

Volumn 32, Issue 5-6, 2001, Pages 409-418

Integration of power devices in advanced mixed signal analog BiCMOS technology

(1) Efland, T R a

a TEXAS INSTRUMENTS (United States)

Author keywords

BiCMOS technology; Power devices; Process roadmaps

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; POWER ELECTRONICS;

PROCESS ROADMAPS;

CMOS INTEGRATED CIRCUITS;

EID: 0035334218 PISSN: 00262692 EISSN: None Source Type: Journal
DOI: 10.1016/S0026-2692(01)00011-8 Document Type: Article

Times cited : (15)

References (25)

1
- 0031617961
- ISPSD
- (1998) Smart power approaches VLSI complexity , pp. 11-16
- Contiero, C.¹

2
- 0004910778
- IEDM
- (1996) Characteristics and applications of a 0.6 μm bipolar-CMOS-DMOS technology combining VLSI non-volatile memories , pp. 465-468
- Contiero, C.¹

3
- 0031374479
- BCTM
- (1997) A 0.7 μm linear BiCMOS/DMOS technology for mixed-signal/power applications , pp. 155-157
- Smith, J.¹

4
- 84886448038
- IEDM
- (1997) 16 to 60 V rated LDMOS show advanced performance in an 0.72 μm evolution BiCMOS power technology , pp. 367-370
- Tsai, C.¹

5
- 0034447764
- ISPSD
- (2000) A 0.35 μm CMOS based smart power technology for 7 V-50 V applications , pp. 317-320
- Parthasarathy, V.¹

6
- 0034448282
- ISPSD
- (2000) LDMOS implementation in a 0.35 μm BCD technology (BCD6) , pp. 323-326
- Moscatelli, A.¹

7
- 0004912561
- ISPSD
- (2000) 2 Resurf LDMOS in a 0.35 μm CMOS process , pp. 335-338
- Zhu, R.¹

8
- 0034450033
- ISPSD
- (2000) Low voltage CMOS compatible power MOSFET for on-chip DC/DC convertors , pp. 43-48
- Nassif-khalil, S.G.¹

9
- 0031634388
- ISPSD
- (1998) 2 n-channel LDMOS in a 0.65 μm smart power technology for 20-30 V applications , pp. 61-64
- Parthasarathy, V.¹

10
- 84907897000
- ESSDERC (HV-SOI, power, density)
- (1999) Trend and issues in BCD smart power technologies , pp. 111-118
- Contiero, C.¹

11
- 0004844687
- ISPSD
- (1996) LDMOS implantation by large tilt implant in 0.6 μm BCD5, FLASH MemoryCompatible , pp. 75-78
- Contiero, C.¹

12
- 0028754593
- IEDM
- (1994) Optimized complimentary 40 V power LDMOS-Fets use existing fabrication steps in submicron CMOS technology , pp. 399-402
- Efland, T.¹

13
- 0031618281
- ISPSD
- (1998) Analysis of high current breakdown and UIS behavior of RESURF LDMOS (RLDMOS) devices , pp. 419-422
- Pendharkar, S.¹

14
- 0004907749
- IEDM
- (1992) An optimized Resurf LDMOS power device module compatible with advanced logic process , pp. 963-966
- Efland, T.¹

15
- 0029716646
- ISPSD
- (1996) sp vs BV performance , pp. 147-150
- Efland, T.¹

16
- 0030658212
- ISPSD
- (1997) A performance comparison between new reduced surface drain RSD LDMOS and RESURF and conventional planar power devices rated at 20 V , pp. 185-188
- Efland, T.¹

17
- 0004878673
- IEDM
- (1996) 2 very thin Resurf (VTR), drain extended IGFETS in a compressed BiCMOS process , pp. 469-472
- Tsai, C.Y.¹

18
- 0004871565
- IEDM
- (1999) 20 V and 8 V lateral trench gate power MOSFETs with record-low on-resistance , pp. 197-2000
- Kawaguchi, Y.¹

19
- 0034449948
- ISPSD
- (2000) 2 , pp. 47-50
- Nakagawa, A.¹

20
- 0034447761
- ISPSD
- (2000) Folded gate LDMOS with low on-resistance and high transconductance , pp. 55-59
- Xu, S.¹

21
- 0034449647
- ISPSD
- (2000) A review of RESURF technology , pp. 11-18
- Ludikhuize, A.W.¹

22
- 0004897524
- IEDM
- (1999) Lateral thinking about power devices (LDMOS) , pp. 679-682
- Efland, T.¹

23
- 0004842678
- VDE, June
- (2000) Safe operating area performance of IC output drivers - system and application needs
- Hower, P.¹

24
- 0034449710
- ISPSD
- (2000) Using adaptive RESURF to improve the SOA of LDMOS transistors , pp. 345-348
- Hower, P.¹

25
- 0034448113
- ISPSD
- (2000) SCR-LDMOS - a novel LDMOS device with ESD robustness , pp. 341-344
- Pendharkar, S.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.