Folded gate LDMOS with low on-resistance and high transconductance

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2000, Pages 55-56

  Xu, S ^a   Zhu, Y ^a   Foo, P D ^a   Liang, Y C ^a   Sin, J K O ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CONTACTS; ELECTRIC RESISTANCE; MOSFET DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; TRANSCONDUCTANCE;

BREAKDOWN VOLTAGE; CHANNEL DENSITY; CONTACT HOLE STRUCTURE; FOLDED GATE STRUCTURE; TRANSCONDUCTANCE ENHANCEMENT;

MOS DEVICES;

EID: 0034447761     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A 33V, 0.25μm-cm2 n-channel LDMOS in a 0.65μm smart power technology for 20-30V applications
2. 16-60V rated LDMOS show advanced performance in an 0.72μm evolution BiCMOS power technology
3. Efficiency of power devices using full Cu metallisation technologies
4. Self-aligned RESURF to LOCOS region LDMOS characterisation shows excellent Rsp vs BV performance
5. A trench lateral power MOSFET using self-aligned trench bottom contact holes
6. New 3-D lateral power MOSFETs with ultra low on-resistance