Experimental determination of the maximum post-process annealing temperature for standard CMOS wafers

IEEE Transactions on Electron Devices

Volumn 48, Issue 2, 2001, Pages 377-385

  Sedky, S ^a  

^a CAIRO UNIVERSITY   (Egypt)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; LEAKAGE CURRENTS; MICROELECTROMECHANICAL DEVICES; SEMICONDUCTING ALUMINUM COMPOUNDS; SILICON WAFERS; THERMAL EFFECTS; TUNGSTEN;

INTERCONNECTION LAYERS; POSTPROCESSING TEMPERATURES;

CMOS INTEGRATED CIRCUITS;

EID: 0035249549     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.902741     Document Type: Article

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