Parallel genetic algorithms for simulation-based sequential circuit test generation

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1997, Pages 475-481

  Krishnaswamy, D ^a   Hsiao, M S ^a   Saxena, V ^a   Rudnick, E M ^a   Patel, J H ^a   Banerjee, P ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; GENETIC ALGORITHMS; PARALLEL ALGORITHMS; SEQUENTIAL CIRCUITS;

TEST GENERATION;

VLSI CIRCUITS;

EID: 0030838136     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)