Algorithms for switch level delay fault simulation

IEEE International Test Conference (TC)

Volumn , Issue , 1997, Pages 982-991

  Bose, Soumitra ^a   Agrawal, Vishwani D ^a   Szymanski, Thomas G ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; LOGIC CIRCUITS; MOS DEVICES; VECTORS;

SWITCH LEVEL DELAY FAULT SIMULATION;

COMPUTER AIDED NETWORK ANALYSIS;

EID: 0031338829     PISSN: 10893539     EISSN: None     Source Type: None    
DOI: 10.1109/TEST.1997.639714     Document Type: Conference Paper

References (15)

1. R. E. Bryant A Switch-Level Model and Simulator for MOS Digital Systems IEEE Transactions on Computers 33 160 177 February 1984
2. A. Pierzynska S. Pilarski Non-Robust versus Robust Proc. International Test Conference 123 131 Proc. International Test Conference 1995-October
3. P. Franco E. J. McCluskey Three Pattern Tests for Delay Faults Proc. 12th IEEE VLSI Test Symposium 452 456 Proc. 12th IEEE VLSI Test Symposium 1994-May
4. A. V. Aho J. E. Hopcroft J. D. Ullman The Design and Analysis of Computer Algorithms 1974 Addison-Wesley MA, Residing
5. P. Agrawal S. H. Robinson T. G. Szymanski Automatic Modeling of Switch-Level Networks Using Partial Orders IEEE Transactions on Computer Aided Design 9 696 707 July 1990
6. S. Bose P. Agrawal V. D. Agrawal Logic Systems for Path Delay Test Generation Proc. EURODAC 200 205 Proc. EURODAC 1993-September
7. S. Bose P. Agrawal V. D. Agrawal Generation of Compact Delay Tests by Multiple Path Activation Proc. International Test Conference 714 723 Proc. International Test Conference 1993-October
8. J. Rajski H. Cox Stuck-Open and Transition Fault Testing in CMOS Complex Gates Proc. International Test Conference 688 694 Proc. International Test Conference 1988-September
9. J. P. Hayes Pseudo-Boolean Logic Circuits IEEE Transactions on Computers c-35 602 612 July 1986
10. J. P. Hayes An Introduction to Switch-Level Modeling IEEE Design & Test of Computers 4 18 25 August 1987
11. R. E. Bryant A Survey of Switch-Level Algorithms IEEE Design & Test of Computers 4 26 40 August 1987
12. G. L. Smith Model for Delay Faults Based upon Paths Proc. International Test Conference 342 349 Proc. International Test Conference 1985-September
13. K. J. Lee C. A. Njinda M. A. Breuer SWiTEST: A Switch-Level Test Generation System for CMOS Combinational Circuits IEEE Transactions on Computer Aided Design 13 625 637 May 1995
14. S. C. Ma E. J. McCluskey Open Faults in BiCMOS Circuits IEEE Transactions on Computer Aided Design 13 567 575 May 1995
15. S. Bose P. Agrawal V. D. Agrawal Path Delay Fault Simulation of Sequential Circuits IEEE Transactions on VLSI Systems 1 453 461 December 1993