Novel spectral methods for built-in self-test in a system-on-a-chip environment

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 163-168

  Giani, A ^a   Sheng, S ^a   Hsiao, M S ^a   Agrawal, V D ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; EMBEDDED SYSTEMS; FAILURE ANALYSIS; MICROPROCESSOR CHIPS; RANDOM PROCESSES; REAL TIME SYSTEMS; SPECTRUM ANALYSIS;

EMBEDDED PROCESSOR; HADAMARD COEFFICIENTS; SYSTEM-ON-A-CHIP; WEIGHTED RANDOM PATTERNS;

INTEGRATED CIRCUIT TESTING;

EID: 0034994832     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (31)

1. Built-in test for complex digital integrated circuits
2. When to use random testing
3. Fixed-biased pseudorandom built in self test for random pattern resistant circuits
4. Structure and technique for pseudo random-based testing of sequential circuits
5. Calculation of multiple sets of weights for weighted random testing
6. Multiple distributions for biased random test patterns
7. Self-test using unequiprobable random patterns
8. A new procedure for weighted random built-in self-test
9. Generating deterministic unordered test patterns with counter
10. Test set embedding in a built-in self-test environment
11. A novel pattern generator for near-perfect fault coverage
12. LFSR-coded test patterns for scan designs
13. Generation of vector patterns through reseeding of multiple polynomial linear feedback shift registers
14. An efficient BIST scheme based on reseeding of multiple polynomial linear feedback shift registers
15. Test embedding with discrete logarithms
16. On calculating efficient LFSR seeds for built-in self-test
17. Testing by verifying walsh coefficients
18. The use of Rademacher-Walsh spectrum in random compact testing
19. Arithmetic built-in-self-test for DSP cores
20. Mixed-mode BIST using embedded processors
21. Accumulator based deterministic BIST
22. DEFUSE: A deterministic functional self-test methodology for processors
23. Correlation analysis of compacted test vectors and the use of correlated vectors for test generation
24. Correlation-based test generation for sequential circuits
25. Vector restoration based static compaction of test sequences for synchronous sequential circuits
26. Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration
27. Combinational profiles of sequential benchmark circuits
28. ITC '99 benchmark circuits - Preliminary results