Microanalysis of VLSI interconnect failure modes under short-pulse stress conditions

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2000, Pages 283-288

  Banerjee, Kaustav ^a   Kim, Dae Yong ^a   Amerasekera, Ajith ^a   Hu, Chenming ^a   Wong, S Simon ^a   Goodson, Kenneth E ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM ALLOYS; CURRENT DENSITY; ELECTRIC DISCHARGES; ELECTRIC RESISTANCE; ELECTROMIGRATION; ELECTROSTATICS; FAILURE ANALYSIS; GRAIN SIZE AND SHAPE; INTEGRATED CIRCUIT TESTING; RAPID SOLIDIFICATION; STRESSES; TRANSMISSION ELECTRON MICROSCOPY;

ELECTROSTATIC DISCHARGES (ESD); INTERCONNECT FAILURE MODES;

VLSI CIRCUITS;

EID: 0033751599     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (11)