State-of-the-art issues for technology and circuit design of ESD protection in CMOS ICs

Semiconductor Science and Technology

Volumn 11, Issue 6, 1996, Pages 833-850

  Duvvury, Charvaka ^a   Amerasekera, Ajith ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; ELECTROSTATIC COATINGS; INTEGRATED CIRCUIT LAYOUT; PERFORMANCE; PROCESS ENGINEERING; PROTECTION; RELIABILITY;

CIRCUIT DESIGN;

CMOS INTEGRATED CIRCUITS;

EID: 0030169203     PISSN: 02681242     EISSN: None     Source Type: Journal    
DOI: 10.1088/0268-1242/11/6/001     Document Type: Review

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