RAM diagnostic tests

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 1996, Pages 100-102

  Yarmolik, V N ^a   Klimets, Yu V ^a   Van De Goor, A J ^b   Demidenko, S N ^c  

^a BELARUSIAN STATE UNIVERSITY OF INFORMATICS AND RADIOELECTRONICS   (Belarus)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c SINGAPORE POLYTECHNIC   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DIAGNOSTIC ABILITY; DIAGNOSTIC CAPABILITIES; DIAGNOSTIC TESTS; FAULT COVERAGES; FOLLOWING PROBLEM; MARCH TESTS;

RANDOM ACCESS STORAGE;

EID: 84948700603     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.1996.782499     Document Type: Conference Paper

References (5)

1. R. Treuer, V. Agarwal. Fault Location Algorithms for Repairable Embedded RAMs. IEEE International Workshop on Memory Testing, Design and Technology. 1993., pp. 55-60.
2. L. Shen, B. Cockbum. An Optimal March Test for Locating Faults in DRAMs. IEEE International Workshop on Memory Testing, Design and Technology. 1993. pp. 61-66.
3. H. Ritter, B. Muller. Built-in Test Processor For Self-Testing Repairable RAM. IEEE International Test Conference, 1987, paper 45.3, pp. 1078-1084.
4. G. Gaydadjiev and A. van de Goor. An Analysis of Linked Faults. Technical report No. 1-68340-44(1995)08, Delft University of Technology, 1995.
5. Van de Goor A.J., Gavdadjiev G.N., Yarmolik V.N., Mikitjuk V.G. March E: More Efficient RAM Test with Higher Fault Coverage // Proc. IEEE VLSI Test Symposium - April 1996, Princeton, New Jersey, USA.