Recent progress and future prospects of SOI CMOS

Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)

Volumn 83, Issue 10, 2000, Pages 24-34

  Tsuchiya, Toshiaki ^a  

^a SHIMANE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LSI CIRCUITS; MICROPROCESSOR CHIPS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY;

MINIATURIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 0034294091     PISSN: 8756663X     EISSN: None     Source Type: Journal    
DOI: 10.1002/1520-6432(200010)83:10<24::AID-ECJB4>3.0.CO;2-9     Document Type: Article

References (36)

1. The National Technology Roadmap for Semiconductors, 1997 Edition. SIA (Semiconductor Industry Association).
2. 2 layers formed by oxygen implantation into silicon. Electron Lett 1978;14:593-594.
3. Nakashima S, Izumi K. Practical reduction of dislocation density in SIMOX wafers. Electron Lett 1990;26:1647-1649.
4. Nakashima S, Katayama T, Miyamura Y, Matsuzaki A, Imai M, Izumi K, Ohwada N. Thickness increment of buried oxide in a SIMOX wafer by high-temperature oxidation. Proc IEEE Int SOI Conf, p 71-72, 1994.
5. Yonehara T, Sakaguchi K, Sato N. Epitaxial layer transfer by bond and etch back of porous Si. Appl Phys Lett 1994;64:2108-2110.
6. Bruel M. Silicon on insulator material technology. Electron Lett 1995;31:1201-1202.
7. Maszara WP. Silicon-on-insulator material for deep submicron technologies. Ext Abstr SSDM, p 294-295, 1998.
8. En WG, Malik IJ, Bryan A, Farrens S, Henley FJ, Cheung NW, Chan C. The genesis process: A new SOI wafer fabrication method. Proc IEEE Int SOI Conf, p 163-164, 1998.
9. Colinge JP. Reduction of kink effect in thin-film SOI MOSFET's. IEEE Electron Devices Lett 1988;9:97-99.
10. Kato K, Taniguchi K. Numerical analysis of switching characteristic in SOI MOSFET's. IEEE Trans Electron Devices 1986;33:133-139.
11. Maeda S, Yamaguchi Y, Kim IJ, Iwamatsu T, Ipposhi T, Miyamoto S, Maegawa S, Ueda K, Nii K, Mashiko K, Inoue Y, Nishimura T, Miyoshi H. Analysis of delay time instability according to the operating frequency in field shield isolated SOI circuits. IEEE Trans Electron Devices 1998;45:1479-1486.
12. Munteanu D, Weiser DA, Cristoloveanu S, Faynot D, Pelloie JL, Fossum JG. Generation-recombination transient effects in partially depleted SOI transistors: Systematic experiments and simulations. IEEE Trans Electron Devices 1998;45:1678-1683.
13. Tsuchiya T, Ohno T, Kado Y. Present status and potential of subquarter-micron ultra-thin-film CMOS/SIMOX technology. Proc 6th Int Symp on SOI Technology and Devices, ECS 1994;94:401-412.
14. Tsuchiya T. Stability and reliability of fully-depleted SOI MOSFET's. Proc SPIE Symp on Microelectronic Manufacturing 1996;2875:16-27.
15. Yoshimi M, Terauchi M, Murakoshi A, Takahashi M, Matsuzawa K, Shigyo N, Ushiku Y. Technology trends of silicon-on-insulator - Its advances and problems to be solved. IEDM Tech Dig, p 429-432, 1994.
16. Tsuchiya T, Ohno T, Tazawa S, Tomizawa M. Suppression of parasitic bipolar action and improvement of hot-carrier reliability in fully-depleted metal-oxide-semiconductor field effect transistors on SIMOX (Separation by Implanted Oxygen) introducing recombination centers near source junction. Jpn J Apply Phys 1997;36:6175-6180.
17. Ohno T, Takahashi M, Ohtaka A, Sakakibara Y, Tsuchiya T. Suppression of the parasitic bipolar effect in ultra-thin-film nMOSFETs/SIMOX by Ar ion implantation into source/drain regions. IEDM Tech Dig, p 627-630, 1995.
18. Horiuchi M, Tamura M. BESS: A source structure that fully suppresses the floating body effects in SOI CMOSFETs. IEDM Tech Dig, p 121-124, 1996.
19. Yamaguchi Y, Ishibashi A, Shimizu M, Nishimura T, Tsukamoto K, Horie K, Akasaka Y. A high-speed 0.6-μm 16 K CMOS gate array on a thin SIMOX film. IEEE Trans Electron Devices 1993;40:179-186.
20. Tsuchiya T, Ohno T. New hot-carrier-degradation mode in thin-film SOI nMOSFET's. IEEE Electron Device Lett 1995;16:427-429.
21. Tsuchiya T, Ohno T, Kado Y, Kai J. Hot-carrier-injected oxide region in front and back interfaces in ultra-thin (50 nm), fully depleted, deep-submicron NMOS and PMOSFET's/SIMOX and their hot-carrier immunity. IEEE Trans Electron Devices 1994;41:2351-2356.
22. Ohtomo Y, Mizusawa T, Nishimura K, Sawada H, Ino M. A quarter-micron SIMOX-CMOS LVTTL-compatible gate array with an over 2,000 V ESD-protection circuit. Proc IEEE Custom Integrated Circuit Conf, p 57-60, 1996.
23. Kado Y, Inokawa H, Okazaki Y, TsuchiyaT, Kawai Y, Sato M, Sakakibara Y, Nakayama S, Yamada H, Kitamura M, Nakashima S, Nishimura K, Date S, Ino M, Takeya K, Sakai T. Substantial advantages of fully-depleted CMOS/SIMOX devices as low-power high-performance VLSI components compared with its bulk-CMOS counterpart. IEDM Tech Dig, p 635-638, 1995.
24. Kado Y, Ohno T, Harada M, Deguchi K, Tsuchiya T. Enhanced performance of multi-GHz PLL LSIs using sub-1/4-micron gate ultrathin film CMOS/SIMOX technology with synchrotron X-ray lithography. IEDM Tech Dig, p 243-246, 1993.
25. Ino M, Sawada H, Nishimura K, Urano M, Suto H, Date S, Ishihara T, Takeda T, Kȧdo Y, Inokawa H, Tsuchiya T, Sakakibara Y, Arita Y, Izumi K, Takeya K, Sakai T. 0.25 μm CMOS/SIMOX gate array LSI. ISSCC Dig Tech Pap, p 86-87, 1996.
26. Ohtomo Y, Yasuda S, Nogawa M, Inoue J, Yamakoshi K, Sawada H, Ino M, Hino S, Sato Y, Takei Y, Watanabe T, Takeya K. A 40 Gb/s 8 × 8 ATM switch LSI using 0.25 μm CMOS/SIMOX. ISSCC Dig Pap, p 154, 1997.
27. Oashi T, Eimori T, Morishita F, Iwamatsu T, Yamaguchi Y, Okuda F, Shimomura K, Shimano H, Sakashita N, Arimoto K, Inoue Y, Komori S, Inuishi M, Nishimura T, Miyoshi H. 16 Mb DRAM/SOI technologies for sub-1 V operation. IEDM Tech Dig, p 609-612, 1996.
28. Mizuno T, Toriumi A, Iwase M, Takahashi M, Niyama H, Fukumoto M, Yoshimi M. Hot-carrier effects in 0.1 μm gate length CMOS devices. IEDM Tech Dig, p 695-698, 1992.
29. Tsuchiya T, Sato Y, Tomizawa M. Three mechanisms determining short-channel effects in fully-depleted SOI MOSFET's. IEEE Trans Electron Devices 1998;45:1116-1121.
30. Tsuchiya T, Saito Y, Tomizawa Y. Study on parasitic resistance between source and channel in ultra-thin film SOI MOSFETs. Extended Abstracts (45th Spring Meeting, 1998); Japan Society of Applied Physics, 30p-YB-7.
31. Sekigawa T, Hayashi Y. Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate. Solid-State Electron 1984;27:827-828.
32. Shimatani T, Pidin S, Koyanagi M. New electrically-thinned intrinsic-channel SOI MOSFET with 0.01 μm channel length. Ext Abstr SSDM, p 494-496, 1996.
33. Assaderaghi F, Parke S, Sinitsky D, Bokor J, Ko PK, Hu C. A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation. IEEE Electron Devices Lett 1994;15:510-512.
34. Douseki T, Shigematsu S, Tanabe Y, Harada M, Inokawa H, Tsuchiya T. A 0.5 V SIMOX-MTCMOS circuit with 200 ps logic gate. ISSCC Dig Tech Pap, p 84-85, 1996.
35. Welser J, Hoyt JL, Takagi S, Gibbons JF. Strain dependence of the performance enhancement is strained-Si n-MOSFETs. IEDM Tech Dig, p 373-376, 1994.
36. Rim K, Welser J, Hoyt JL, Gibbons JF. Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs. IEDM Tech Dig, p 517-520, 1995.