Effects of interface traps in silicon-quantum-dots-based memory structures

Physica E: Low-Dimensional Systems and Nanostructures

Volumn 8, Issue 2, 2000, Pages 189-193

  Xiaoli, Yuan ^a   Yi, Shi ^a   Shulin, Gu ^a   Jianmin, Zhu ^a   Youdou, Zheng ^a   Kenichi, Saito ^b   Hiroki, Ishikuro ^b   Toshiro, Hiramoto ^b  

^a NANJING UNIVERSITY   (China)

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; ELECTRON TRAPS; MOS DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR QUANTUM DOTS; VOLTAGE MEASUREMENT;

INTERFACE TRAPS;

SEMICONDUCTOR STORAGE;

EID: 0034248131     PISSN: 13869477     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1386-9477(00)00138-7     Document Type: Article

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