-
1
-
-
0018678393
-
A monolithic video A/D converter
-
Dec
-
J. G. Peterson, “A monolithic video A/D converter,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 932–937, Dec. 1979.
-
(1979)
IEEE J. Solid-State Circuits
, vol.SC-14
, pp. 932-937
-
-
Peterson, J.G.1
-
2
-
-
0025450397
-
A 10 b 75 MHz subranging ADC
-
Feb
-
B. Zojer, B. Astegher, H. Jessner, and R. Petschacher. “A 10 b 75 MHz subranging ADC,” in ISSCC Dig. Tech. Papers, Feb. 1990. pp. 164–165.
-
(1990)
ISSCC Dig. Tech. Papers
, pp. 164-165
-
-
Zojer, B.1
Astegher, B.2
Jessner, H.3
Petschacher, R.4
-
3
-
-
0026397041
-
A 10 bit 75 mega-sample per second A/D converter
-
J. Marsh, K. Lofstrom, H. J. Engert, and B. Price, “A 10 bit 75 mega-sample per second A/D converter,” in Proc. Custom Integrated Circuits Conf., 1991, pp. 26.6.1-26.6.4
-
(1991)
Proc. Custom Integrated Circuits Conf.
, pp. 26.6.1-26.6.4
-
-
Marsh, J.1
Lofstrom, K.2
Engert, H.J.3
Price, B.4
-
4
-
-
0026206282
-
A wide-band 10-b 20-Ms/s pipelined ADC using current-mode signals
-
Aug
-
P. Real, D. H. Robertson, C. W. Mangelsdorf, and T. L. Tewksbury, “A wide-band 10-b 20-Ms/s pipelined ADC using current-mode signals,” IEEE J. Solid-State Circuits, vol. 26, pp. 1103–1109, Aug. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, pp. 1103-1109
-
-
Real, P.1
Robertson, D.H.2
Mangelsdorf, C.W.3
Tewksbury, T.L.4
-
5
-
-
0025450133
-
A 10 b 30 MHz two-step parallel BiCMOS ADC with internal S/H
-
Feb
-
A. Matsuzawa et al., “A 10 b 30 MHz two-step parallel BiCMOS ADC with internal S/H,” in ISSCC Dig. Tech. Papers, Feb. 1990, pp. 162–163.
-
(1990)
ISSCC Dig. Tech. Papers
, pp. 162-163
-
-
Matsuzawa, A.1
-
6
-
-
0025562755
-
A 10-b 15-MHz CMOS recycling two-step A/D converter
-
Dec
-
B.-S. Song, S.-H. Lee, and M. F. Tompsett, “A 10-b 15-MHz CMOS recycling two-step A/D converter,” IEEE J. Solid-State Circuits. vol. 25, pp. 1328–1338, Dec. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, pp. 1328-1338
-
-
Song, B.-S.1
Lee, S.-H.2
Tompsett, M.F.3
-
7
-
-
33645560030
-
A high-speed, high accuracy pipeline A/D converter
-
K. Martin, “A high-speed, high accuracy pipeline A/D converter,” in Proc. Asilomar Conf. Circuits Syst., Computers, 1981, pp. 489–492.
-
(1981)
Proc. Asilomar Conf. Circuits Syst., Computers
, pp. 489-492
-
-
Martin, K.1
-
8
-
-
0022113342
-
High-accuracy pipeline A/D converter configuration
-
Aug
-
G. C. Temes, “High-accuracy pipeline A/D converter configuration,” Electron. Lett., pp. 762–763, Aug. 1985.
-
(1985)
Electron. Lett.
, pp. 762-763
-
-
Temes, G.C.1
-
9
-
-
0023599417
-
A pipelined 5-Msamples/s 9-bit analog-to-digital converter
-
Dec
-
S. H. Lewis and P. R. Gray, “A pipelined 5-Msamples/s 9-bit analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 954–961, Dec. 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.SC-22
, pp. 954-961
-
-
Lewis, S.H.1
Gray, P.R.2
-
10
-
-
0024122159
-
A pipelined 13-bit, 250-ks/s, 5-V analog-to-digital converter
-
Dec
-
S. Sutarja and P. R. Gray, “A pipelined 13-bit, 250-ks/s, 5-V analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 23. pp. 1316–1323, Dec. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, pp. 1316-1323
-
-
Sutarja, S.1
Gray, P.R.2
-
11
-
-
0024122160
-
A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter
-
Dec
-
B.-S. Song, M. F. Tompsett, and K. R. Lakshmikumar, “A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter,” IEEE J. Solid-State Circuits, vol. 23, pp. 1324–1333, Dec. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, pp. 1324-1333
-
-
Song, B.-S.1
Tompsett, M.F.2
Lakshmikumar, K.R.3
-
12
-
-
4344606309
-
Video-rate analog-to-digital conversion using pipelined architectures
-
Univ. California, Berkeley. Memo. UCB/ERL M87/90. Nov
-
S. H. Lewis, “Video-rate analog-to-digital conversion using pipelined architectures,” Univ. California, Berkeley, Memo. UCB/ERL M87/90, Nov. 1987.
-
(1987)
-
-
Lewis, S.H.1
-
13
-
-
0002806838
-
High-performance parallel-serial analog to digital converter with error correction
-
(New York), Mar
-
G. G. Gorbatenko, “High-performance parallel-serial analog to digital converter with error correction,” in IEEE Nat. Conv. Rec. (New York), Mar. 1966.
-
(1966)
IEEE Nat. Conv. Rec
-
-
Gorbatenko, G.G.1
-
14
-
-
0002797545
-
A 150 Mbps A/D and D/A conversion system
-
O. A. Horna “A 150 Mbps A/D and D/A conversion system,” Comstat Tech. Rev., vol. 2, no. 1, pp. 52–57, 1972.
-
(1972)
Comstat Tech. Rev.
, vol.2
, Issue.1
, pp. 52-57
-
-
Horna, O.A.1
-
15
-
-
25744470506
-
High speed analog-to-digital conversion in integrated circuits
-
Univ. California, Berkeley
-
S. Taylor, “High speed analog-to-digital conversion in integrated circuits,” Ph.D. dissertation, Univ. California, Berkeley, pp. 30–42, 1978.
-
(1978)
Ph.D. dissertation
, pp. 30-42
-
-
Taylor, S.1
-
16
-
-
84941431348
-
-
communication private
-
M. Snelgrove, private communication.
-
-
-
Snelgrove, M.1
-
17
-
-
8344233312
-
A 1-bit/cycle algorithmic analog-to-digital converter without high-precision comparators
-
Univ. California, Berkeley. Memo. UCB/ERL M90/69, Aug
-
G. Jusuf, “A 1-bit/cycle algorithmic analog-to-digital converter without high-precision comparators,” Univ. California, Berkeley. Memo. UCB/ERL M90/69, Aug. 1990
-
(1990)
-
-
Jusuf, G.1
-
18
-
-
0026402676
-
A pipelined 9-stage video-rate analog-to-digital converter
-
S. H. Lewis, H. S. Fetterrnan, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, “A pipelined 9-stage video-rate analog-to-digital converter,” in Proc. Custom Integrated Circuits Conf., 1991, pp. 26.4.1-26.4.4
-
(1991)
Proc. Custom Integrated Circuits Conf.
, pp. 26.4.1-26.4.4
-
-
Lewis, S.H.1
Fetterrnan, H.S.2
Gross, G.F.3
Viswanathan, T.R.4
-
19
-
-
12944292363
-
High-resolution pipelined analog-to-digital conversion
-
Univ. California, Berkeley„ Memo. UCB/ERL M88/27, May
-
S. Sutarja, “High-resolution pipelined analog-to-digital conversion,” Univ. California, Berkeley„ Memo. UCB/ERL M88/27, May 1988, pp. 40–42.
-
(1988)
, pp. 40-42
-
-
Sutarja, S.1
-
20
-
-
0026141224
-
A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS
-
Apr
-
Y.-M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS,” IEEE J. Solid-State Circuits, vol. 26, pp. 628–636, Apr. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, pp. 628-636
-
-
Lin, Y.-M.1
Kim, B.2
Gray, P.R.3
-
22
-
-
0020920315
-
High-frequency CMOS switched-capacitor filters for communications application
-
Dec
-
T. C. Choi et al., “High-frequency CMOS switched-capacitor filters for communications application,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 652–664, Dec. 1983.
-
(1983)
IEEE J. Solid-Stare Circuits
, vol.SC-18
, pp. 652-664
-
-
Choi, T.C.1
-
23
-
-
84941452102
-
-
private communication
-
P. R. Gray, private communication.
-
-
-
Gray, P.R.1
-
24
-
-
0024749617
-
A fully differential sample-and-hold circuit for high-speed applications
-
Dec
-
G. Nicollini, P. Confalonieri, and D. Senderowicz, “A fully differential sample-and-hold circuit for high-speed applications,” IEEE J. Solid-State Circuits, vol. 24, pp. 1461–1465, Dec. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1461-1465
-
-
Nicollini, G.1
Confalonieri, P.2
Senderowicz, D.3
-
25
-
-
0020267942
-
A family of differential NMOS analog circuits for a PCM codec filter chip
-
Dec
-
D. Senderowicz, S. F. Dreyer, J. H. Huggins, C. F. Rahim, and C. A. Laber, “A family of differential NMOS analog circuits for a PCM codec filter chip,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1014–1023, Dec. 1982.
-
(1982)
IEEE J. Solid-State Circuits
, vol.SC-17
, pp. 1014-1023
-
-
Senderowicz, D.1
Dreyer, S.F.2
Huggins, J.H.3
Rahim, C.F.4
Laber, C.A.5
-
26
-
-
0013010167
-
MOS cascade current mirror
-
U.S. Patent 4 550 284 Oct
-
N. S. Sooch, “MOS cascade current mirror,” U.S. Patent 4 550 284, Oct. 1985.
-
-
-
Sooch, N.S.1
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