A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter

IEEE Journal of Solid-State Circuits

Volumn 30, Issue 3, 1995, Pages 166-172

  Cho, Thomas Byunghak ^a   Gray, Paul R ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COMPUTER CIRCUITS; ELECTRIC LOSSES; NYQUIST DIAGRAMS; OPERATIONAL AMPLIFIERS; SIGNAL DISTORTION; SIGNAL TO NOISE RATIO;

CHARGE PUMP CIRCUITS; CIRCUIT TECHNIQUES; DIGITAL CORRECTIONS; LOW VOLTAGE MIXED SIGNAL SYSTEM ENVIRONMENTS;

ANALOG TO DIGITAL CONVERSION;

EID: 0029269932     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.364429     Document Type: Article

References (8)

1. K. Kusumoto et al., “A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC,” in ISSCC Dig. Tech. Pap., Feb. 1993, pp. 62–63.
2. M. Ito et al., “A 10-b 20-Ms/s 3 V-supply CMOS A/D converter for integration into system VLSIs,” in ISSCC Dig. Tech. Pap., Feb. 1994, pp. 48–49.
3. T. Matsuura et al., “A 95-mW, 10-b 15-MHz low-power CMOS ADC using analog double-sampled pipelining scheme,” in VLSI Symp. Dig. Tech. Pap., 1992, pp. 98–99.
4. S. H. Lewis et al., “10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 351–358, Mar. 1992.
5. Y. M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5 MHz self-calibrated pipelined A/D converter in 3-µm CMOS,” IEEE J. Solid-State Circuits, vol. 26, pp. 628–636, Apr. 1991.
6. K. Bult and G. J. G. M. Geelen, “A fast-settling CMOS opamp with 90-dB dc gain and 116 MHz unity-gain frequency,” in ISSCC Dig. Tech. Pap., Feb. 1990, pp. 108–109.
7. Y. Nakagome et al., “Experimental 1.5-V 64-Mb DRAM,” IEEE J. Solid-State Circuits, vol. 26, pp. 465–472, Apr. 1991.
8. G. Jusuf, “A 1-bit/cycle algorithmic analog-to-digital converter without high-precision comparators,” Electron. Res. Lab., Univ. of California, Berkeley, Memo. UCB/ERL M90/69, Aug. 1990.