Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 23, Issue 1, 2000, Pages 39-47

  Nemoto, Kazunori ^a   Akcali, Elif ^b   Uzsoy, Reha M ^b  

^a HITACHI LTD   (Japan)

^b SCHOOL OF INDUSTRIAL ENGINEERING   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COST EFFECTIVENESS; FAILURE ANALYSIS; MATHEMATICAL MODELS; PRODUCTIVITY; QUALITY CONTROL; YIELD STRESS;

CYCLE TIME REDUCTION; PRODUCT LIFE CYCLES; SEMICONDUCTOR WAFER FABRICATION;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0033750593     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/6104.827525     Document Type: Article

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