-
1
-
-
33746095622
-
-
Res. Rep. ESRC 88-20, University of California, Berkeley, CA
-
Adiga, S., and Glassey, C. R., “Object-Oriented Simulation to Support Research in Manufacturing," Res. Rep. ESRC 88-20, University of California, Berkeley, CA (1988).
-
(1988)
“Object-Oriented Simulation to Support Research in Manufacturing,"
-
-
Adiga, S.1
Glassey, C.R.2
-
2
-
-
0024914678
-
Validated Simulation Models for Factory Control
-
Burlingame, CA
-
Atherton, R. W., and Pool, M. A., "Validated Simulation Models for Factory Control," Proceedings of the First International Semiconductor Manufacturing Science Symposium, Burlingame, CA (1989).
-
(1989)
Proceedings of the First International Semiconductor Manufacturing Science Symposium
-
-
Atherton, R.W.1
Pool, M.A.2
-
3
-
-
84952199886
-
A Product Design Problem in Semiconductor Manufacturing
-
forthcoming
-
Avram, F., and Wein, L. M., “A Product Design Problem in Semiconductor Manufacturing,” Operations Research, forthcoming (1989).
-
(1989)
Operations Research
-
-
Avram, F.1
Wein, L.M.2
-
4
-
-
0039649384
-
-
VLSI Memo No. 89-518, Massachusetts Institute of Technology (April
-
Bai, X., and Gershwin, S. B., “A Manufacturing Scheduler’s Perspective on Semiconductor Fabrication," VLSI Memo No. 89-518, Massachusetts Institute of Technology (April 1990).
-
(1990)
A Manufacturing Schedulers Perspective on Semiconductor Fabrication,"
-
-
Bai, X.1
Gershwin, S.B.2
-
5
-
-
84941534070
-
-
MIT Microsystems Research Center, VLSI Memo No. 90-604 June
-
Bai, X., Srivatsan, N., and Gershwin, S. B., “Scheduling Manufacturing Systems with Work-in-Process Inventory: Single Part Type Systems," MIT Microsystems Research Center, VLSI Memo No. 90-604 (June 1990).
-
(1990)
“Scheduling Manufacturing Systems with Work-In-Process Inventory: Single Part Type Systems,"
-
-
Bai, X.1
Srivatsan, N.2
Gershwin, S.B.3
-
6
-
-
0025532680
-
Scheduling Manufacturing Systems with Work-in-Process Inventory: Nonlinear Formulation of Single Part Type Systems
-
Hawaii (December
-
Bai, X., Srivatsan, N., and Gershwin, S. B., “Scheduling Manufacturing Systems with Work-in-Process Inventory: Nonlinear Formulation of Single Part Type Systems,” Proceedings of the 29th IEEE Conference on Decision and Control, Hawaii (December 1990).
-
(1990)
Proceedings of the 29Th IEEE Conference on Decision and Control
-
-
Bai, X.1
Srivatsan, N.2
Gershwin, S.B.3
-
7
-
-
84941534070
-
-
Research Report OR 230-90, Massachusetts Institute of Technology (October
-
Bai, S. X., and Gershwin, S. B., “Scheduling Manufacturing Systems with Work-in-Process Inventory Control: Multiple Part Type Systems," Research Report OR 230-90, Massachusetts Institute of Technology (October 1990).
-
(1990)
“Scheduling Manufacturing Systems with Work-In-Process Inventory Control: Multiple Part Type Systems,"
-
-
Bai, S.X.1
Gershwin, S.B.2
-
8
-
-
0025536790
-
-
Proceedings Ninth IEEE International Electronics Manufacturing Technology Symposium, Washington DCOctober
-
Bai, X., Srivatsan, N., and Gershwin, S. B., “Hierarchical Realtime Scheduling of a Semiconductor Fabrication Facility,” Proceedings Ninth IEEE International Electronics Manufacturing Technology Symposium, Washington DC (October 1990).
-
(1990)
Hierarchical Realtime Scheduling of a Semiconductor Fabrication Facility
-
-
Bai, X.1
Srivatsan, N.2
Gershwin, S.B.3
-
9
-
-
0026397443
-
-
Proceedings of the 1991 Winter Simulation Conference, B. L. Nelson, W. D. Kelton, G. M. Clark (eds.)
-
Baum, S. S., and O’Donnell, C. M., “An Approach to Modeling Labor and Machine Down Time in Semiconductor Fabrication," Proceedings of the 1991 Winter Simulation Conference, B. L. Nelson, W. D. Kelton, G. M. Clark (eds.), 448-454 (1991).
-
(1991)
“An Approach to Modeling Labor and Machine down Time in Semiconductor Fabrication,"
, pp. 448-454
-
-
Baum, S.S.1
O’Donnell, C.M.2
-
11
-
-
0019590377
-
Hierarchical Production Planning: A Single Stage System
-
Bitran, G. R., Haas, E. A., and Has, A. C., "Hierarchical Production Planning: A Single Stage System,” Operations Research, Vol. 29, No. 4, 717-743 (1981).
-
(1981)
Operations Research
, vol.29
, Issue.4
, pp. 717-743
-
-
Bitran, G.R.1
Haas, E.A.2
Has, A.C.3
-
12
-
-
0020103083
-
Hierarchical Production Planning: A Two-Stage System
-
Bitran, G. R., Haas, E. A., andHax, A. C., "Hierarchical Production Planning: A Two-Stage System,” Operations Research, Vol. 30, No. 2, 232-251 (1982).
-
(1982)
Operations Research
, vol.30
, Issue.2
, pp. 232-251
-
-
Bitran, G.R.1
Haas, E.A.2
Hax, A.C.3
-
13
-
-
0024667686
-
CAM Software: Its Getting Better,"
-
May
-
Burggraaf, P., “CAM Software: It’s Getting Better," Semiconductor International, 72-80 (May 1988).
-
(1988)
Semiconductor International
, pp. 72-80
-
-
Burggraaf, P.1
-
14
-
-
0022748217
-
Performance Analysis Techniques for IC Manufacturing Lines
-
Burman, D. Y., Gurrola-Gal, F. J., Nozari, A., Sathaye, S., and Sitarik, J. P., “Performance Analysis Techniques for IC Manufacturing Lines,” AT&T Bell Labs Technical Journal, Vol. 65, 46-56 (1986).
-
(1986)
At&T Bell Labs Technical Journal
, vol.65
, pp. 46-56
-
-
Burman, D.Y.1
Gurrola-Gal, F.J.2
Nozari, A.3
Sathaye, S.4
Sitarik, J.P.5
-
15
-
-
0023981636
-
Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication
-
Chen, H., Harrison, J. M., Mandelbaum, A., Van Ackere, A., and Wein, L. M., "Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication,” Operations Research, Vol. 36, No. 2, 202-215 (1988).
-
(1988)
Operations Research
, vol.36
, Issue.2
, pp. 202-215
-
-
Chen, H.1
Harrison, J.M.2
Mandelbaum, A.3
Van Ackere, A.4
Wein, L.M.5
-
17
-
-
0002474498
-
Close the Marketing/Manufacturing Gap
-
Crittenden, V. L., “Close the Marketing/Manufacturing Gap,” Sloan Management Review, Vol. 33, 41-52 (1992).
-
(1992)
Sloan Management Review
, vol.33
, pp. 41-52
-
-
Crittenden, V.L.1
-
18
-
-
0025433611
-
The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing
-
Cunningham, J. A., “The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 3, No. 2, 60-72 (1990).
-
(1990)
IEEE Transactions on Semiconductor Manufacturing
, vol.3
, Issue.2
, pp. 60-72
-
-
Cunningham, J.A.1
-
19
-
-
0002958880
-
Simulation of VLSI Manufacturing Areas
-
Dayhoff, J. E., and Atherton, R. W., “Simulation of VLSI Manufacturing Areas,” VLSI Design, 84-92 (December 1984).
-
(1984)
VLSI Design
, pp. 84-92
-
-
Dayhoff, J.E.1
Atherton, R.W.2
-
20
-
-
0022984672
-
Signature Analysis of Dispatch Schemes in Wafer Fabrication
-
Dayhoff, J. E., and Atherton, R. W., “Signature Analysis of Dispatch Schemes in Wafer Fabrication," IEEE Transactions on Components. Hybrids and Manufacturing Technology, Vol. 9, No. 4, 518-525 (1986).
-
(1986)
IEEE Transactions on Components. Hybrids and Manufacturing Technology
, vol.9
, Issue.4
, pp. 518-525
-
-
Dayhoff, J.E.1
Atherton, R.W.2
-
21
-
-
0022992279
-
Signature Analysis: Simulation of Inventory, Cycle Time and Throughput Tradeoffs in Wafer Fabrication
-
Dayhoff, J. E., and Atherton, R. W., “Signature Analysis: Simulation of Inventory, Cycle Time and Throughput Tradeoffs in Wafer Fabrication," IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 9, No. 4, 498-507 (1986).
-
(1986)
IEEE Transactions on Components
, vol.9
, Issue.4
, pp. 498-507
-
-
Dayhoff, J.E.1
Atherton, R.W.2
-
22
-
-
0025843946
-
Manufacturing Capacity and its Measurement: A Critical Evaluation
-
Elmaghraby, S. E., “Manufacturing Capacity and its Measurement: A Critical Evaluation," Computers and Operations Research, Vol. 18, 615-627 (1991).
-
(1991)
Computers and Operations Research
, vol.18
, pp. 615-627
-
-
Elmaghraby, S.E.1
-
23
-
-
0011596389
-
Useof Nonfmancial Performance Measures
-
Spring
-
Fisher, J., “Useof Nonfmancial Performance Measures,” Journal of Cost Management, 31-38 (Spring 1992).
-
(1992)
Journal of Cost Management
, pp. 1-38
-
-
Fisher, J.1
-
24
-
-
24544445231
-
-
Technical Report No. T91016, Semiconductor Research Corporation, Research Triangle Park, NC 27709
-
Fowler, J. W., “Strategic Control of Multichannel Bulk Server Diffusion/Oxidation Processes,” Technical Report No. T91016, Semiconductor Research Corporation, Research Triangle Park, NC 27709 (1990).
-
(1990)
Strategic Control of Multichannel Bulk Server Diffusion/Oxidation Processes
-
-
Fowler, J.W.1
-
26
-
-
0022094177
-
Short-term Production Scheduling of an Automated Manufacturing Facility
-
Gershwin, S. B., Akella, R., and Choong, Y. F., “Short-term Production Scheduling of an Automated Manufacturing Facility," IBM Joumalof Research and Development, Vol. 29, No. 4, 392-400 (1985).
-
(1985)
IBM Joumalof Research and Development
, vol.29
, Issue.4
, pp. 392-400
-
-
Gershwin, S.B.1
Akella, R.2
Choong, Y.F.3
-
27
-
-
84952224200
-
-
Res. Rep. ESRC-89-24, University of California, Berkeley
-
Glassey, C. R., “An Overview of BLOCS/M, The Berkeley Library of Objects for Control and Simulation of Manufacturing," Res. Rep. ESRC-89-24, University of California, Berkeley (1989).
-
(1989)
“An Overview of BLOCS/M, the Berkeley Library of Objects for Control and Simulation of Manufacturing,"
-
-
Glassey, C.R.1
-
28
-
-
0023964289
-
Closed-Loop Job Release Control for VLSI Circuit Manufacturing
-
Glassey, C. R., and Resende, M.G.C., “Closed-Loop Job Release Control for VLSI Circuit Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 1, 36-46 (1988).
-
(1988)
IEEE Transactions on Semiconductor Manufacturing
, vol.1
, Issue.1
, pp. 36-46
-
-
Glassey, C.R.1
Resende, M.G.2
-
29
-
-
0024102409
-
A Scheduling Rule for Job Release in Semiconductor Fabrication
-
Glassey, C. R., and Resende, M.G.C., “A Scheduling Rule for Job Release in Semiconductor Fabrication,” Operations Research Letters, Vol. 7, No. 5, 213-217 (1988).
-
(1988)
Operations Research Letters
, vol.7
, Issue.5
, pp. 213-217
-
-
Glassey, C.R.1
Resende, M.G.C.2
-
30
-
-
0004873564
-
The Use of Bottleneck Starvation Avoidance with Queue Predictions in Shop Floor Control
-
Res. Rep. ESRC 89-23, University of California, Berkeley
-
Glassey, C. R., and Petrakian, R. G., “The Use of Bottleneck Starvation Avoidance with Queue Predictions in Shop Floor Control," Res. Rep. ESRC 89-23, University of California, Berkeley (1989).
-
(1989)
-
-
Glassey, C.R.1
Petrakian, R.G.2
-
31
-
-
0022712939
-
A Total Framework for Semiconductor Production Planning and Scheduling
-
May
-
Golovin, J. J., “A Total Framework for Semiconductor Production Planning and Scheduling,” Solid State Technology, 167-170 (May 1986).
-
(1986)
Solid State Technology
-
-
Golovin, J.J.1
-
32
-
-
84952233031
-
-
Proceedings Simulation and Artificial Intelligence in Manufacturing, Society of Manufacturing Engineers, Long Beach, CA (October
-
Hadavi, K., and Voigt, K., “An Integrated Planning and Scheduling Environment,” Proceedings Simulation and Artificial Intelligence in Manufacturing, Society of Manufacturing Engineers, Long Beach, CA (October 14-16, 1987).
-
(1987)
An Integrated Planning and Scheduling Environment
, pp. 14-16
-
-
Hadavi, K.1
Voigt, K.2
-
33
-
-
0021469319
-
Flexible Material Handling Automation in Wafer Fabrication
-
Harper, J. G., and Bailey, L. G., “Flexible Material Handling Automation in Wafer Fabrication,” Solid State Technology, 89-98 (July 1984).
-
(1984)
Solid State Technology
, pp. 89-98
-
-
Harper, J.G.1
Bailey, L.G.2
-
34
-
-
0003304668
-
Measuring Delivery Performance: A Case Study from the Semiconductor Industry
-
Harrison, J. M., Holloway, C. A., and Patell, J. M., "Measuring Delivery Performance: A Case Study from the Semiconductor Industry,” in Measures for Manufacturing Excellence
-
In Measures for Manufacturing Excellence
-
-
Harrison, J.M.1
Holloway, C.A.2
Patell, J.M.3
-
36
-
-
84952193533
-
-
Technical Report No. 935, Department of Operations Research and Industrial Engineering, Cornell University
-
Heath, D. C., Jackson, P. L., Levesque, K., Fret, M., Tlakula, S., and Akkan, C., "Chip Assignment Algorithms for Dynamic Wafer Design in Semiconductor Manufacturing,” Technical Report No. 935, Department of Operations Research and Industrial Engineering, Cornell University (1990).
-
(1990)
Chip Assignment Algorithms for Dynamic Wafer Design in Semiconductor Manufacturing
-
-
Heath, D.C.1
Jackson, P.L.2
Levesque, K.3
Fret, M.4
Tlakula, S.5
Akkan, C.6
-
37
-
-
0022914444
-
The Future of Automation for High-Volume Wafer Fabrication and ASIC Manufacturing
-
Hughes, R. A., and Shott, J. D., “The Future of Automation for High-Volume Wafer Fabrication and ASIC Manufacturing, ’' Proceedings of the IEEE, Vol. 74, No. 12. 1775-1793 (1986).
-
(1986)
Proceedings of the IEEE
, vol.74
, Issue.12
, pp. 1775-1793
-
-
Hughes, R.A.1
Shott, J.D.2
-
38
-
-
0024919235
-
-
Proceedings of the 1989 Winter Simulation Conference, E. A. MacNair, K. J. Musselman, P. Heidelberger (eds.), 918-921
-
Johri, P. K., “Dispatching in an Integrated Circuit Wafer Fabrication Line,” Proceedings of the 1989 Winter Simulation Conference, E. A. MacNair, K. J. Musselman, P. Heidelberger (eds.), 918-921 (1989).
-
(1989)
Dispatching in an Integrated Circuit Wafer Fabrication Line
-
-
Johri, P.K.1
-
39
-
-
0020915621
-
‘An Algorithm for the Computer Control of a Flexible Manufacturing System
-
Kimemia, J., and Gershwin, S. B., "An Algorithm for the Computer Control of a Flexible Manufacturing System," HE Transactions, Vol. 15, No. 4. 353-362 (1983).
-
(1983)
HE Transactions
, vol.15
, Issue.4
, pp. 353-362
-
-
Kimemia, J.1
Gershwin, S.B.2
-
40
-
-
84952196675
-
-
Faculty of Management, University of Toronto (July
-
Kubiak, W., Lou, S.X.C., and Wang, Y.-M., “Mean Flow Time Minimization in Re-entrant Job Shops with Hub,” Faculty of Management, University of Toronto (July 1990).
-
(1990)
Mean Flow Time Minimization in Re-Entrant Job Shops with Hub
-
-
Kubiak, W.1
Lou, S.X.C.2
Wang, Y.-M.3
-
42
-
-
84952200795
-
-
Department of Industrial Engineering and Operations Research, University of California, Berkeley
-
Leachman, R. C., andCarmon, T. F., “On Capacity Modeling for Production Planning with Alternative Machines," Department of Industrial Engineering and Operations Research, University of California, Berkeley (1991).
-
(1991)
On Capacity Modeling for Production Planning with Alternative Machines,"
-
-
Leachman, R.C.1
Carmon, T.F.2
-
43
-
-
84952254092
-
-
presented at ORSA/TIMS Conference, Vancouver May
-
Leachman, R. C., Solorzano, M., and Glassey, C. R., “A Queue Management Policy for the Release of Factory Work Orders,” presented at ORSA/TIMS Conference, Vancouver (May 1989).
-
(1989)
A Queue Management Policy for the Release of Factory Work Orders
-
-
Leachman, R.C.1
Solorzano, M.2
Glassey, C.R.3
-
44
-
-
84952251299
-
-
Dept, of Industrial Engineering and Operations Research, University of California, Berkeley, CA
-
Leachman, R. C., and Sohoni, V. S., “Automated Shift Scheduling as a Tool for Problem Identification and People Management in Semiconductor Factories,” Dept, of Industrial Engineering and Operations Research, University of California, Berkeley, CA (1990).
-
(1990)
Automated Shift Scheduling as a Tool for Problem Identification and People Management in Semiconductor Factories
-
-
Leachman, R.C.1
Sohoni, V.S.2
-
45
-
-
0002823699
-
Managing Supply Chain Inventory: Pitfalls and Opportunities
-
Lee, H. L., and Billington, C., “Managing Supply Chain Inventory: Pitfalls and Opportunities,” Sloan Management Review, Vol. 33, 65-73 (1992).
-
(1992)
Sloan Management Review
, vol.33
, pp. 65-73
-
-
Lee, H.L.1
Billington, C.2
-
47
-
-
0024765326
-
A Robust Production Control Policy for VLSI Wafer Fabrication
-
Lou, S.X.C., and Kager, P. W., “A Robust Production Control Policy for VLSI Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 2, No. 4,159-164 (1989).
-
(1989)
IEEE Transactions on Semiconductor Manufacturing
, vol.2
, Issue.4
, pp. 159-164
-
-
Lou, S.X.C.1
Kager, P.W.2
-
48
-
-
0026395588
-
-
Proceedings of the 1991 Winter Simulation Conference, B. L. Nelson, W. D. Kelton, G. M. Clark (eds.)
-
Lou, S.X.C., Yan, H., Sethi, S., Gardel, A., and Deosthali, P., “Using Simulation to Test the Robustness of Various Existing Production Control Policies," Proceedings of the 1991 Winter Simulation Conference, B. L. Nelson, W. D. Kelton, G. M. Clark (eds.), 261-269 (1991).
-
(1991)
“Using Simulation to Test the Robustness of Various Existing Production Control Policies,"
, pp. 261-269
-
-
Lou, S.X.C.1
Yan, H.2
Sethi, S.3
Gardel, A.4
Deosthali, P.5
-
49
-
-
0024104839
-
Bottleneck Starvation Indicators for Shop-Floor Control
-
Lozinski, C., and Glassey, C. R., “Bottleneck Starvation Indicators for Shop-Floor Control,” IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 4, 147-153 (1988).
-
(1988)
IEEE Transactions on Semiconductor Manufacturing
, vol.1
, Issue.4
, pp. 147-153
-
-
Lozinski, C.1
Glassey, C.R.2
-
50
-
-
0024480282
-
Applying Just-in-Time in a Wafer Fab
-
Martin-Vega, L. A., Pippin, M., Gerdon, E., and Burcham, R., “Applying Just-in-Time in a Wafer Fab,” IEEE Transactions on Semiconductor Manufacturing, Vol. 2, No. 1, 16-22 (1989).
-
(1989)
IEEE Transactions on Semiconductor Manufacturing
, vol.2
, Issue.1
, pp. 16-22
-
-
Martin-Vega, L.A.1
Pippin, M.2
Gerdon, E.3
Burcham, R.4
-
51
-
-
0024901725
-
-
Proceedings of the 1989 Winter Simulation Conference, E. A. MacNair, K. J. Mussel- man, P. Heidelbergcr, (eds.)
-
Miller, D. L., “Implementing the Results of a Manufacturing Simulation in a Semiconductor Line,” Proceedings of the 1989 Winter Simulation Conference, E. A. MacNair, K. J. Mussel- man, P. Heidelbergcr, (eds.), 922-929 (1989).
-
(1989)
Implementing the Results of a Manufacturing Simulation in a Semiconductor Line
, pp. 922-929
-
-
Miller, D.L.1
-
52
-
-
0343228535
-
Managing Factory Productivity using Object-Oriented Simulation for Setting Shift Production Targets in VLSI Manufacturing
-
3.1-3.14 November
-
Najmi, A., and Lozinski, C., “Managing Factory Productivity using Object-Oriented Simulation for Setting Shift Production Targets in VLSI Manufacturing,” Proceedings of the Autofact Conference, Society of Manufacturing Engineers, 3.1-3.14 (November 1989).
-
(1989)
Proceedings of the Autofact Conference, Society of Manufacturing Engineers
-
-
Najmi, A.1
Lozinski, C.2
-
53
-
-
0020750263
-
Off-Line Quality Control in Integrated Circuit Fabrication Using Experimental Design
-
Phadke, M. S., Kackar, R. N., Speeney, D. V., and Grieco, M. J., “Off-Line Quality Control in Integrated Circuit Fabrication Using Experimental Design,” The Bell System Technical Journal, Vol. 62, No. 5, 1273-1309 (1983).
-
(1983)
The Bell System Technical Journal
, vol.62
, Issue.5
, pp. 1273-1309
-
-
Phadke, M.S.1
Kackar, R.N.2
Speeney, D.V.3
Grieco, M.J.4
-
54
-
-
84952173358
-
SEMATECH: IE at Work in the Trenches to Meet Worldwide Competition
-
December
-
Phillips, D. T., Curry, G. L., Deuermeyer, B. L., Wortman, M., and Sitarik, J., “SEMATECH: IE at Work in the Trenches to Meet Worldwide Competition," Industrial Engineering, 36-44 (December 1989).
-
(1989)
Industrial Engineering
, pp. 36-44
-
-
Phillips, D.T.1
Curry, G.L.2
Deuermeyer, B.L.3
Wortman, M.4
Sitarik, J.5
-
56
-
-
0026213711
-
A Generic Computer Simulation Model to Characterize Photolithography Manufacturing Area in an 1C FAB Facility
-
Prasad, K., “A Generic Computer Simulation Model to Characterize Photolithography Manufacturing Area in an 1C FAB Facility,” IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 14, No. 3, 483-487 (1991).
-
(1991)
IEEE Transactions on Components, Hybrids and Manufacturing Technology
, vol.14
, Issue.3
, pp. 483-487
-
-
Prasad, K.1
-
58
-
-
0020251340
-
An Overview of PANACEA, a Software Package for Analyzing Markovian Queueing Networks
-
Ramakrishnan, K. G., and Mitra, D., “An Overview of PANACEA, a Software Package for Analyzing Markovian Queueing Networks,” Bell System Technical Journal, Vol. 61, No. 10, 2849-2872, (1982).
-
(1982)
Bell System Technical Journal
, vol.61
, Issue.10
, pp. 2849-2872
-
-
Ramakrishnan, K.G.1
Mitra, D.2
-
59
-
-
0021469318
-
Wafer Fabrication and Process Automation Research at Stanford University
-
Reid, B. K., Shott, J. D., and Meindl, J. D., “Wafer Fabrication and Process Automation Research at Stanford University,” Solid State Technology, 126-133 (July 1984).
-
(1984)
Solid State Technology
, pp. 126-133
-
-
Reid, B.K.1
Shott, J.D.2
Meindl, J.D.3
-
62
-
-
0020844913
-
A Unifying View of Hybrid Simulation/Analytic Models and Modeling
-
Shanthikumar, J. G., and Sargent, R. G., “A Unifying View of Hybrid Simulation/Analytic Models and Modeling," Operations Research, Vol. 31. 1030-1052 (1983).
-
(1983)
Operations Research
, vol.31
, pp. 1030-1052
-
-
Shanthikumar, J.G.1
Sargent, R.G.2
-
63
-
-
0025396652
-
"Planning for Production of a Set of Components when Yeld is Random,” IEEE Transactions on Components
-
Singh, M. R., Abraham, C. T., and Akella, R., "Planning for Production of a Set of Components when Yeld is Random,” IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 13. 103-108 (1990).
-
(1990)
Hybrids and Manufacturing Technology
, vol.13
, pp. 103-108
-
-
Singh, M.R.1
Abraham, C.T.2
Akella, R.3
-
64
-
-
84952232688
-
-
presented at Technical Program of the Southwest Semiconductor and Electronics Exposition, Phoenix, AZ
-
Smith, M., and Pujari, A., “Animation and Simulation Methodology for Plastic Dual-In-Line Package Manufacturing,”presented at Technical Program of the Southwest Semiconductor and Electronics Exposition, Phoenix, AZ (1987).
-
(1987)
Animation and Simulation Methodology for Plastic Dual-In-Line Package Manufacturing
-
-
Smith, M.1
Pujari, A.2
-
68
-
-
0002350057
-
-
Interfaces
-
Sullivan, G., and Fordyce, K., “IBM Burlington’s Logistics Management System,” Interfaces, Vol. 20, No. 1,43-64 (1990).
-
(1990)
IBM Burlingtons Logistics Management System,”
, vol.20
, Issue.1
, pp. 43-64
-
-
Sullivan, G.1
Fordyce, K.2
-
69
-
-
0003679027
-
-
McGraw-Hill, New York
-
Sze, S. M., VLSI Technology, McGraw-Hill, New York (1983).
-
(1983)
VLSI Technology
-
-
Sze, S.M.1
-
70
-
-
84952239398
-
-
Research Report, School of Industrial Engineering, Purdue University (
-
Uzsoy, R., Lee, C. Y., and Martin-Vega, L. A., “A Survey of Production Planning and Scheduling Models in the Semiconductor Industry Part Q: Shop-Floor Control,” Research Report, School of Industrial Engineering, Purdue University (1992).
-
(1992)
A Survey of Production Planning and Scheduling Models in the Semiconductor Industry Part Q: Shop-Floor Control
-
-
Uzsoy, R.1
Lee, C.Y.2
Martin-Vega, L.A.3
-
72
-
-
0024055865
-
Scheduling Semiconductor Wafer Fabrication
-
Wein, L. M., “Scheduling Semiconductor Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 3, 115-129 (1988).
-
(1988)
IEEE Transactions on Semiconductor Manufacturing
, vol.1
, Issue.3
, pp. 115-129
-
-
Wein, L.M.1
-
73
-
-
0001200692
-
Due-Date Setting and Priority Sequencing in a Multiclass M/G/l Queue
-
Wein, L. M., “Due-Date Setting and Priority Sequencing in a Multiclass M/G/l Queue,” Management Science, Vol. 37, No. 7, 834-850 (1991).
-
(1991)
Management Science
, vol.37
, Issue.7
, pp. 834-850
-
-
Wein, L.M.1
-
74
-
-
0026869951
-
On the Relationship Between Yield and Cycle Time in Semiconductor Wafer Fabrication
-
Wein, L. M., “On the Relationship Between Yield and Cycle Time in Semiconductor Wafer Fabrication," IEEE Transactions on Semiconductor Manufacturing, Vol. 5, 156-158 (1992).
-
(1992)
IEEE Transactions on Semiconductor Manufacturing
, vol.5
, pp. 156-158
-
-
Wein, L.M.1
-
75
-
-
0020848139
-
-
Whitt, W.,“The Queueing Network Analyzer," Bell System Technical Journal, Vol. 62, No. 9, 2779-2815 (1983).
-
(1983)
“The Queueing Network Analyzer," Bell System Technical Journal
, vol.62
, Issue.9
, pp. 2779-2815
-
-
Whitt, W.1
-
76
-
-
84952240860
-
-
Research Report T91014, Semiconductor Research Corporation, Research Triangle Park, NC 27709
-
Wise, K. D., “Automation in Semiconductor Manufacturing,” Research Report T91014, Semiconductor Research Corporation, Research Triangle Park, NC 27709 (1990).
-
(1990)
Automation in Semiconductor Manufacturing
-
-
Wise, K.D.1
-
77
-
-
84943676094
-
-
Technical Report No.89-16, Department of Industrial and Operations Engineering, The University of Michigan, Ann Arbor (1989), presented at Technical Program of the Southwest Semiconductor and Electronics Exposition, Phoenix, AZ
-
Yano, C. A., and Lee, H. L., “Lot-Sizing with Random Yields: A Review,” Technical Report No.89-16, Department of Industrial and Operations Engineering. The University of Michigan, Ann Arbor (1989).presented at Technical Program of the Southwest Semiconductor and Electronics Exposition, Phoenix, AZ (1987).
-
(1987)
Lot-Sizing with Random Yields: A Review
-
-
Yano, C.A.1
Lee, H.L.2
-
81
-
-
0002350057
-
-
Interfaces
-
Sullivan, G., and Fordyce, K., “IBM Burlington’s Logistics Management System,” Interfaces, Vol. 20, No. 1,43-64 (1990).
-
(1990)
IBM Burlington’s Logistics Management System
, vol.20
, Issue.1
, pp. 43-64
-
-
Sullivan, G.1
Fordyce, K.2
-
82
-
-
0003679027
-
-
McGraw-Hill, New York
-
Sze, S. M., VLSI Technology, McGraw-Hill, New York (1983).
-
(1983)
VLSI Technology
-
-
Sze, S.M.1
-
83
-
-
84952239398
-
-
Research Report, School of Industrial Engineering, Purdue University (
-
Uzsoy, R., Lee, C. Y., and Martin-Vega, L. A., "A Survey of Production Planning and Scheduling Models in the Semiconductor Industry Part II: Shop-Floor Control,” Research Report, School of Industrial Engineering, Purdue University (1992).
-
(1992)
"A Survey of Production Planning and Scheduling Models in the Semiconductor Industry Part II: Shop-Floor Control,”
-
-
Uzsoy, R.1
Lee, C.Y.2
Martin-Vega, L.A.3
-
85
-
-
0024055865
-
Scheduling Semiconductor Wafer Fabrication
-
Wein, L. M., “Scheduling Semiconductor Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. I, No. 3, 115-129 (1988).
-
(1988)
IEEE Transactions on Semiconductor Manufacturing
, vol.1
, Issue.3
, pp. 115-129
-
-
Wein, L.M.1
-
86
-
-
0001200692
-
Due-Date Setting and Priority Sequencing in a Multiclass M/G/l Queue
-
Wein, L. M., “Due-Date Setting and Priority Sequencing in a Multiclass M/G/l Queue,” Management Science, Vol. 37, No. 7, 834-850 (1991).
-
(1991)
Management Science
, vol.37
, Issue.7
, pp. 834-850
-
-
Wein, L.M.1
-
87
-
-
0026869951
-
On the Relationship Between Yield and Cycle Time in Semiconductor Wafer Fabrication
-
Wein, L. M., “On the Relationship Between Yield and Cycle Time in Semiconductor Wafer Fabrication," IEEE Transactions on Semiconductor Manufacturing, Vol. 5, 156-158 (1992).
-
(1992)
IEEE Transactions on Semiconductor Manufacturing
, vol.5
, pp. 156-158
-
-
Wein, L.M.1
-
88
-
-
0020848139
-
-
Whitt, W.,“The Queueing Network Analyzer," Bell System Technical Journal, Vol. 62, No. 9, 2779-2815 (1983).
-
(1983)
“The Queueing Network Analyzer," Bell System Technical Journal
, vol.62
, Issue.9
, pp. 2779-2815
-
-
Whitt, W.1
-
89
-
-
84952240860
-
-
Research Report T91014, Semiconductor Research Corporation, Research Triangle Park, NC 27709
-
Wise, K. D., “Automation in Semiconductor Manufacturing,” Research Report T91014, Semiconductor Research Corporation, Research Triangle Park, NC 27709 (1990).
-
(1990)
Automation in Semiconductor Manufacturing
-
-
Wise, K.D.1
-
90
-
-
84943676094
-
-
Technical Report No.89-16, Department of Industrial and Operations Engineering, The University of Michigan, Ann Arbor
-
Yano, C. A., and Lee, H. L., “Lot-Sizing with Random Yields: A Review,” Technical Report No.89-16, Department of Industrial and Operations Engineering. The University of Michigan, Ann Arbor (1989).
-
(1989)
Lot-Sizing with Random Yields: A Review
-
-
Yano, C.A.1
Lee, H.L.2
|