Design of future single wafer logic fabs

Proceedings of the IEEE/CPMT International Electronic Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 1995, Pages 283-285

  Castrucci, Paul ^a  

^a Paul Castrucci & Associates Inc ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLEAN ROOMS; CMOS INTEGRATED CIRCUITS; COSTS; ELECTRONICS INDUSTRY; INTEGRATED CIRCUIT MANUFACTURE; PROCESS ENGINEERING; SEMICONDUCTOR MATERIALS; STANDARDS;

CMOS LOGIC PRODUCTS; MANUFACTURING CYCLE TIME; MICRON TECHNOLOGY WAFER; MINIENVIRONMENT TECHNOLOGY; SINGLE WAFER LOGIC FAB DESIGN; WAFER PROCESSING;

LOGIC DESIGN;

EID: 0029537455     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)