Empirical results on the relationship between die yield and cycle time in semiconductor wafer fabrication

IEEE Transactions on Semiconductor Manufacturing

Volumn 9, Issue 2, 1996, Pages 273-277

  Cunningham, Sean P ^a   Shanthikumar, J George ^b  

^a INTEL CORPORATION   (United States)

^b DEPARTMENT OF INDUSTRIAL ENGINEERING AND OPERATIONS RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; COMPUTER SIMULATION; CORRELATION METHODS; DECISION MAKING; MATHEMATICAL MODELS; PRODUCTION CONTROL; SILICON WAFERS;

AGGREGATE DIE YIELD; CYCLE TIME; LOT BY LOT ANALYSIS; SEMICONDUCTOR WAFER FABRICATION;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0030150578     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.492822     Document Type: Article

References (10)

1. K. A. Brownlee, Statistical Theory and Methodology in Science and Engineering, 2nd Ed. New York: Wiley, 1967.
2. Competitive Semiconductor Manufacturing Program, The Competitive Semiconductor Manufacturing Survey: First Report on Results of the Main Phase, R. Leachman, Ed., ESRC/CSM-02. Univ. of California, Berkeley, 1993.
3. D. Dance and R. Jarvis, "Using yield models to accelerate learning curve progress," IEEE Trans. Semicond. Manufact., vol. 5, no. 1, pp. 41-45, 1992.
4. D. Freedman et al., Statistics. New York: W. W. Norton, 1978.
5. C. R. Glassey and M. G. C. Resende, "Closed-loop job release control for VLSI, circuit manufacturing," IEEE Trans. Semicond. Manufact., vol. 1, no. 1, pp. 36-46, 1988.
6. R. W. Hall, Attaining Manufacturing Excellence. Homewood, IL: Dow Jones-Irwin, 1987.
7. R. J. Markle, D. L. Dance, and V. B. Menon, "Employing yield models, in situ monitoring to predict and achieve defect-density goals," Microcontamination, vol. 10, no. 2, pp. 37-41, 1992.
8. C. Meyer, Fast Cycle Time. New York: Free Press, 1993.
9. R. Uszoy et al., "A review of production planning and scheduling models in the semiconductor industry, Part I: System characteristics, performance evaluation, and production planning," IIE Trans., vol. 24, no. 4, pp. 47-60, 1992.
10. L. M. Wein, "On the relationship between yield and cycle time in semiconductor wafer fabrication," IEEE Trans. Semicond. Manufact., vol. 5, no. 2, pp. 156-158, 1992.