Alternative facility layouts for semiconductor wafer fabrication facilities

Proceedings of the IEEE/CPMT International Electronic Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 1995, Pages 384-388

  Hase, Rieko ^a   Uzsoy, Reha ^a   Takoudis, Christos G ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COSTS; DEPOSITION; FAILURE (MECHANICAL); MACHINERY; MAINTENANCE; PERFORMANCE; SCHEDULING; SEMICONDUCTOR DEVICE MANUFACTURE;

CELLULAR LAYOUT; EPITAXIAL DEPOSITION; MACHINE BREAKDOWN; PROCESS LAYOUT; SEMICONDUCTOR WAFER FABRICATION FACILITY; SETUP TIMES;

PLANT LAYOUT;

EID: 0029520114     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)