On the design robustness of threshold logic gates using multi-input floating gate MOS transistors

IEEE Transactions on Electron Devices

Volumn 47, Issue 6, 2000, Pages 1231-1240

  Luck, A ^a   Jung, S ^a   Brederlow, R ^b   Thewes, R ^b   Weber, W ^a   Goser, K ^a  

^a TU DORTMUND UNIVERSITY   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC POTENTIAL; INTEGRAL EQUATIONS; LOGIC DESIGN; LOGIC GATES; MOSFET DEVICES; PARAMETER ESTIMATION; THRESHOLD LOGIC;

ARRAY TEST STRUCTURE; INPUT OFFSET VOLTAGE; MULTI INPUT FLOATING GATE;

LOGIC CIRCUITS;

EID: 0033731346     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.842967     Document Type: Article

References (18)

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