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Volumn , Issue , 1998, Pages 324-327

A low-power and high-performance CMOS fingerprint sensing and encoding architecture

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITIVE FINGERPRINT SENSORS; ENCODING ARCHITECTURE; HIGH-PERFORMANCE CMOS; IMAGE PROCESSING ALGORITHM; LOW-POWER DISSIPATION; MASSIVE PARALLELISM; PERSON IDENTIFICATION; SIMULATIONS AND MEASUREMENTS;

EID: 0013316067     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.1998.186274     Document Type: Conference Paper
Times cited : (3)

References (8)
  • 1
    • 0031070241 scopus 로고    scopus 로고
    • A 390dpi live fingerprint imager based on feedback capacitive sensing scheme
    • M. Tartagni and R. Guerrieri. A 390dpi Live Fingerprint Imager Based on Feedback Capacitive Sensing Scheme. In ISSCC, Digest of Technical Papers, pages 200-201, 1997.
    • (1997) ISSCC, Digest of Technical Papers , pp. 200-201
    • Tartagni, M.1    Guerrieri, R.2
  • 2
    • 0031706872 scopus 로고    scopus 로고
    • A robust, 1.8v 250/iw direct-contact 500dpi fingerprint sensor
    • D. Inglis et al. A Robust, 1.8V 250/iW Direct-Contact 500dpi Fingerprint Sensor. In ISSCC, Digest of Technical Papers, pages 284-285, 1998.
    • (1998) ISSCC, Digest of Technical Papers , pp. 284-285
    • Inglis, D.1
  • 4
    • 0030191040 scopus 로고    scopus 로고
    • An analysis of hexagonal thinning algorithms and skeletal representations
    • R.C. Staunton. An Analysis of Hexagonal Thinning Algorithms and Skeletal Representations. Pattern Recognition, 29:1131-1146, 1997.
    • (1997) Pattern Recognition , vol.29 , pp. 1131-1146
    • Staunton, R.C.1
  • 6
    • 27944492851 scopus 로고
    • A functional mos transistor featuring gate-level weighted sum and threshold operations
    • T. Shibata and T. Ohmi. A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations. IEEE Trans. Electron Devices, 39:1444-1455, 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , pp. 1444-1455
    • Shibata, T.1    Ohmi, T.2
  • 7
    • 0030270806 scopus 로고    scopus 로고
    • On the application of the neuron mos transistor principle for modem vlsi design
    • W. Weber, S.J. Prange, R. Thewes, E. Wohlrab, and A. Luck. On The Application of the Neuron MOS Transistor Principle for Modem VLSI Design. IEEE Trans. Electron Devices, 43:1700-1708, 1996.
    • (1996) IEEE Trans. Electron Devices , vol.43 , pp. 1700-1708
    • Weber, W.1    Prange, S.J.2    Thewes, R.3    Wohlrab, E.4    Luck, A.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.