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Volumn 1991-January, Issue , 1991, Pages 919-922
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An intelligent MOS transistor featuring gate-level weighted sum and threshold operations
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Author keywords
Circuit testing; Hardware; Integrated circuit technology; Logic circuits; Logic devices; MOS devices; MOSFET circuits; Neurons; Silicon; Voltage
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Indexed keywords
COMPUTER HARDWARE;
DIGITAL TO ANALOG CONVERSION;
ELECTRIC POTENTIAL;
ELECTRON DEVICES;
ELECTRONIC EQUIPMENT TESTING;
FIELD EFFECT TRANSISTORS;
HARDWARE;
INTEGRATED CIRCUIT TESTING;
LOGIC CIRCUITS;
LOGIC DEVICES;
MOS DEVICES;
MOSFET DEVICES;
NEURONS;
RECONFIGURABLE HARDWARE;
SEMICONDUCTING SILICON;
SILICON;
TRANSISTORS;
CAPACITIVE COUPLINGS;
CIRCUIT TESTING;
EXPERIMENTAL VERIFICATION;
INTEGRATED CIRCUIT TECHNOLOGY;
MOSFET CIRCUITS;
SOFT-HARDWARE-LOGIC;
THRESHOLD OPERATION;
VARIABLE THRESHOLDS;
COMPUTER CIRCUITS;
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EID: 84954088099
PISSN: 01631918
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/IEDM.1991.235276 Document Type: Conference Paper |
Times cited : (95)
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References (0)
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